Memory Sub-Plane Verify Counting for Faster Fail-Bit Detection
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Solution Overview
Problem
Existing memory devices face challenges in reducing the execution duration of Verify Failbit Count (VFC) operations, which affects chip operation time, and the large area occupied by the VFC circuit reduces the adaptability and increases production costs due to the high utilization rate of peripheral circuits.
Innovation Solution
The memory device performs verify operations on multiple memory sub-planes simultaneously to obtain a verify result and determine the number of fail bits, utilizing a page buffer array and a verify counting circuit to sense and sum fail bit currents, thereby reducing VFC execution duration and peripheral circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If verify operations are performed on multiple memory sub-planes sequentially, then the VFC circuit area can be reduced, but the execution duration of VFC operations increases
Solution Approach 1:
The patent merges multiple verify operations into a single unified operation. Specifically, it combines verify operations for multiple memory sub-planes (e.g., sub-plane 0 and sub-plane 1) into one simultaneous operation, allowing the VFC circuit to process all sub-planes in parallel rather than sequentially. This merging approach reduces the execution duration while the shared circuit design keeps the area occupied minimal.
Solution Approach 2:
The VFC circuit is designed with multi-functionality to handle verify operations for multiple memory sub-planes simultaneously. The circuit uses shared resources including common bit lines (BL0-BL3), common page buffers, and a unified verify counting mechanism that can process results from multiple sub-planes in parallel, making the circuit versatile and efficient.
2Productivity
If the VFC circuit occupies large area, then verification operations can be performed on multiple sub-planes simultaneously, but the adaptability in size between peripheral circuit and memory cell array is reduced and production costs increase
Solution Approach 1:
The patent merges the verify operation functionality across multiple sub-planes into a single integrated VFC circuit. Instead of having separate verify circuits for each sub-plane, the design combines them into one shared circuit that processes multiple sub-planes simultaneously using common bit lines and page buffers, thereby reducing overall circuit area while maintaining high productivity.
Solution Approach 2:
The VFC circuit is designed as a universal multi-functional unit that can handle verify operations for any combination of memory sub-planes. The circuit uses multiplexed resources and configurable control logic to adapt to different verification scenarios, enhancing size adaptability between the peripheral circuit and memory cell array while keeping production costs low.
3Duration of action of moving object
If verify operations are performed on multiple memory sub-planes at the same time, then the chip operation duration is shortened, but the peripheral circuit utilization rate increases
Solution Approach 1:
The patent merges multiple verify operations into a single simultaneous operation across multiple sub-planes. The VFC circuit combines results from multiple sub-planes in one processing cycle, reducing chip operation duration. The merging approach shares circuit resources efficiently, managing complexity while achieving parallel processing benefits.
Solution Approach 2:
The verify counting circuit operates continuously to accumulate fail bit counts from multiple sub-planes simultaneously. The circuit maintains continuous operation throughout the verify process, processing results from all activated sub-planes in parallel without idle periods, thereby shortening overall operation duration while efficiently utilizing circuit resources.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach shortens the chip operation duration, enhances the adaptability in size between the peripheral circuit and memory cell array, and lowers production costs by optimizing the utilization rate of the peripheral circuit.
Implementation Method 1
each page buffer is configured to sense a fail bit current of the coupled memory sub-plane through the bit line
Implementation Method 2
the comparator is configured to: compare the at least one reference current and the sum of the fail bit currents, and output the verify result
Data Source
AI summary
A memory device includes: a memory cell array including a memory plane, wherein the memory plane includes a plurality of memory sub-planes; and a peripheral circuit coupled with the memory cell array and configured to: perform verify operations on the plurality of memory sub-planes at the same time, to obtain a verify result for the memory plane; and determine the number of fail bits of the memory plane based on the verify result.