Integrated Circuit Layout Using Sub-Poly M1 Pitch for Pin Access
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Solution Overview
Problem
In advanced integrated circuit nodes, the rectangular shape of connection pins and polysilicon lines limits routing resources, as they must be aligned on predefined tracks, restricting the placement of device cells under power lines and reducing available routing resources in the M1 interconnection layer.
Innovation Solution
The M1 line pitch is reduced to a ratio less than the polysilicon line pitch, allowing multiple cell layouts to ensure M1 lines fall on tracks, with the M0 layer used for pin access, freeing up M1 routing resources and enabling cells to be placed under power straps, by optimizing VIA0 enclosure design and using different cell layouts based on the pitch ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If M1 track pitch is set to match polysilicon line pitch (1:1 ratio), then connection pins can be located on M1 layer, but M1 pitch is enlarged and routing resources are reduced
Solution Approach 1:
The patent moves connection pins from the M1 layer to the polysilicon layer, utilizing a different dimensional plane for pin placement. This allows M1 layer to be dedicated to routing without competing with pin locations, effectively separating the functions across layers and increasing routing resource availability.
Solution Approach 2:
The patent extracts the connection pin function from the M1 layer and relocates it to the polysilicon layer. This separation allows the M1 layer to focus exclusively on routing operations, thereby increasing the effective routing resources available in the M1 interconnection layer.
2Ease of operation
If all connection pins are located on M1 layer, then pin access is simplified, but device cells cannot be placed under power lines formed in M1 layer
Solution Approach 1:
The patent utilizes the vertical dimension by placing connection pins in the polysilicon layer rather than confining them to the M1 layer. This enables device cells to be positioned directly under M1 power lines while maintaining pin access through the polysilicon layer, achieving both power line integration and routing flexibility.
Solution Approach 2:
The patent segments the connection pin access function from the power line function in the M1 layer. Connection pins are accessed through the polysilicon layer while power lines remain in the M1 layer, allowing independent optimization of both functions without mutual interference.
3Manufacturing precision
If M1 pitch is enlarged to match polysilicon line pitch, then pin alignment is achieved, but routing resource density decreases
Solution Approach 1:
The patent resolves the alignment issue by moving pin locations to the polysilicon layer where they naturally align with polysilicon lines. This eliminates the need to enlarge M1 pitch for alignment purposes, allowing M1 pitch to maintain its original, more dense configuration optimized for routing.
Data Source
AI summary
An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.