Subrange ADC Circuit With Shared Buffers for Low-DNL Image Sensing
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Solution Overview
Problem
Existing image sensor technologies face challenges in reducing noise, particularly fixed pattern noise, in high-density pixel arrays, which affects image quality and requires accurate correlated double sampling (CDS) to differentiate between signal and reset voltages.
Innovation Solution
The implementation of a subrange analog-to-digital converter (ADC) circuitry with local ramp buffers and bit buffers, which stabilizes the load on bit capacitors and allows for precise correlated double sampling by matching the binary ratio between coarse SAR ADC and fine ramp ADC, reducing differential nonlinearity errors and enabling accurate black level calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels within the array is increased to achieve higher image quality, then the image resolution is improved, but the fixed pattern noise and temporal noise increase
Solution Approach 1:
The patent divides the ADC operation into two separate segments: a first ADC operation that captures the reset signal (dark current noise) and a second ADC operation that captures the signal voltage value (image grey value). By segmenting the measurement process into distinct operations, the patent enables correlated double sampling to effectively separate and eliminate fixed pattern noise from the image data, thereby improving image quality in high-density pixel arrays.
2Object-generated harmful factors
If correlated double sampling is implemented to reduce noise, then the fixed pattern noise is reduced, but the complexity of the ADC circuitry increases
Solution Approach 1:
The patent merges the functionality of multiple bit capacitors into a single shared bit capacitor that serves both the first ADC operation (reset signal conversion) and the second ADC operation (signal voltage value conversion). This merging approach eliminates the need for separate capacitor sets, thereby reducing circuit complexity while maintaining the noise reduction benefits of correlated double sampling.
Solution Approach 2:
The shared bit capacitor is designed to perform multiple functions: it participates in both the first ADC operation for capturing reset signal levels and the second ADC operation for capturing signal voltage values. This multi-functional design reduces the total component count and simplifies the ADC circuitry while enabling effective correlated double sampling for noise reduction.
3Device complexity
If a shared bit capacitor is used for both first and second ADC operations, then the circuit complexity is reduced, but differential nonlinearity errors increase
Solution Approach 1:
The patent employs feedback mechanisms where the results of the first ADC operation (reset signal conversion) are used to correct and refine the second ADC operation (signal voltage value conversion). By feeding back the reset signal information, the system can compensate for differential nonlinearity errors that arise from using a shared bit capacitor, thereby maintaining manufacturing precision while keeping the circuit simple.
Solution Approach 2:
The patent dynamically adjusts operational parameters between the first and second ADC operations, such as switching the coupling configuration of the bit capacitor and modifying the reference voltage levels. These parameter changes optimize the performance of the shared bit capacitor for each specific operation, minimizing differential nonlinearity errors while maintaining circuit simplicity.
Data Source
AI summary
A subrange analog-to-digital converter (ADC) converts analog image signal received from a bitline to a digital signal through an ADC comparator. The comparator is shared by a successive approximation register (SAR) ADC coupled to provide M upper output bits (UOB) of the subrange ADC and a ramp ADC coupled to provide N lower output bits (LOB). The digital-to-analog converter (DAC) of the SAR ADC comprises M buffered bit capacitors connected to the comparator. Each buffered bit capacitor comprises a bit capacitor, a bit buffer, and a bit switch controlled by one of the UOB of the SAR ADC. A ramp buffer is coupled between a ramp generator and a ramp capacitor. The ramp capacitor is further coupled to the same comparator. The implementation of ramp buffer and the bit buffers as well as their sharing of the same kind of buffer reduces differential nonlinear (DNL) error of the subrange ADC.