Subranging ADC Reference Ladder Segmentation for Faster Settling
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Solution Overview
Problem
The two-step subranging ADC architecture faces a speed bottleneck at high sampling rates due to reference settling issues, where the reference ladder's bandwidth is reduced by loading from switches and comparators, limiting conversion rate and resolution.
Innovation Solution
The implementation of a two-step subranging ADC architecture with separate coarse and fine reference ladders, where the coarse reference ladder is static and optimized for low power, and the fine reference ladder is dynamic, allowing independent optimization and reducing loading effects, along with the use of additional track-and-hold stages for extended settling time and pre-charging techniques to facilitate faster reference settling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional single reference ladder is used in two-step subranging ADC architecture, then the device complexity is reduced, but the reference settling time increases and bandwidth is reduced due to loading from switches and comparators
Solution Approach 1:
The reference ladder is divided into two separate ladders: a coarse reference ladder and a fine reference ladder. The coarse reference ladder provides references for the first comparison stage, while the fine reference ladder provides references for the second comparison stage. This segmentation allows each ladder to be optimized independently, with the coarse ladder having fewer taps and lower loading, thus achieving faster settling speed without increasing overall device complexity.
2Productivity
If the sampling rate is increased to improve productivity, then the conversion rate increases, but the reference settling time becomes insufficient within the half clock period
Solution Approach 1:
By segmenting the reference ladder into coarse and fine ladders, the settling requirements are divided into two phases. The coarse reference ladder settles during the first half of the conversion cycle, enabling higher sampling rates. The fine reference ladder then settles during the second phase. This segmentation allows the system to maintain adequate settling time for each phase while achieving higher overall sampling rates.
3Speed
If the reference ladder bandwidth is increased to reduce settling time, then the conversion rate improves, but the chip area and power consumption increase
Solution Approach 1:
The coarse reference ladder is designed with fewer taps and lower resistance values to achieve higher bandwidth and faster settling, while the fine reference ladder can use higher resistance values since it operates at lower speeds. This segmentation allows the high-speed coarse ladder to consume more power only when needed, while the fine ladder consumes less power, achieving high conversion rates without proportionally increasing overall power consumption.
Solution Approach 2:
Different parts of the reference system are given different quality characteristics: the coarse reference ladder has low resistance and high bandwidth to enable fast settling, while the fine reference ladder has higher resistance and lower bandwidth since it operates at reduced speed. This local optimization of quality parameters allows high conversion rates without uniform increases in power consumption across the entire system.
Data Source
AI summary
First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. The coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the coarse references and outputs a coarse output based on the first comparison. A switch matrix includes switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides fine references. A fine ADC performs a second comparison of the input voltage and the fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output.