Subranging SAR ADC Architecture for High Resolution at Lower Power
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in balancing resolution and bandwidth with power consumption, as Delta-Sigma ADCs have limited bandwidth and SAR ADCs require increased power for higher resolution and bandwidth.
Innovation Solution
The proposed ADC system employs a pipelined subranging architecture with a coarse stage reducing accuracy requirements and a fine stage used only for a portion of the conversion period, reducing overall power consumption while maintaining high energy efficiency and linearity, by using a first and second subranging SAR ADC stage with a coarse and fine comparator configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Delta-Sigma ADC architecture is used, then resolution is improved, but bandwidth is limited
Solution Approach 1:
The ADC is divided into multiple parallel stages, each handling a portion of the conversion process. The first stage performs initial conversion at lower resolution, and subsequent stages refine the result, allowing the system to achieve high resolution without limiting the overall bandwidth that would constrain a single-stage Delta-Sigma architecture.
2Speed
If SAR ADC architecture is used, then bandwidth is improved, but power consumption increases for higher resolution
Solution Approach 1:
The conversion process is segmented across multiple stages, where each stage processes a portion of the bits. This allows the system to achieve high resolution without requiring a single SAR converter to process all bits simultaneously, thereby reducing the power consumption associated with high-resolution SAR conversion while maintaining bandwidth.
Solution Approach 2:
The fine stage is activated periodically rather than continuously, operating only during specific phases of the conversion process. This periodic operation reduces the average power consumption while maintaining the necessary conversion rate and resolution performance.
3Productivity
If pipelined SAR ADC is used, then conversion rate is improved, but power consumption remains high
Solution Approach 1:
The fine stage comparator and associated circuitry are activated only during specific conversion phases rather than continuously. This periodic operation maintains the high conversion rate by ensuring the fine stage is ready when needed, while significantly reducing the average power consumption compared to continuously operating fine stages in conventional pipelined SAR ADCs.
Data Source
AI summary
An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits. A controller is coupled to the first and second ADC stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal.