Subranging TDC Clock Interface for Wide-Range Jitter Measurement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock screening techniques fail to provide a unified clock performance circuit that is insensitive to process variations and supports multiple modes for measuring various clock performance metrics such as period jitter, K-cycle jitter, duty-cycle variation, and clock skew, while also requiring high resolution and a wide input frequency range, leading to increased chip area and power consumption.
Innovation Solution
A subranging time-to-digital converter (TDC) that measures the time difference between two clock edges using a combination of slow and fast oscillators, with a clock interface that supports multiple measurement modes, and a robust power supply scheme to minimize the impact of process variations and power fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional flash TDC or Vernier TDC architectures use numerous delay cells to meet high resolution and wide input frequency range requirements, then measurement precision is improved, but chip area and power consumption increase substantially
Solution Approach 1:
The patent divides the time measurement function into two independent segments: a coarse TDC handling large time intervals and a fine TDC handling small time intervals. This segmentation allows each segment to use fewer delay cells while maintaining overall high resolution, thereby reducing chip area compared to a single high-resolution TDC
Solution Approach 2:
The patent transitions from a single-dimensional time measurement approach to a two-dimensional measurement space by combining coarse and fine measurements. The coarse TDC provides the integer portion of time measurement while the fine TDC provides the fractional portion, achieving high resolution without requiring a proportional increase in delay cell count
2Measurement precision
If conventional flash TDC or Vernier TDC architectures use numerous delay cells to meet high resolution and wide input frequency range requirements, then measurement precision is improved, but power consumption increases substantially
Solution Approach 1:
By segmenting the measurement function into coarse and fine TDCs with fewer delay cells each, the total power consumption is reduced since power consumption in delay-cell-based TDCs is directly proportional to the number of delay cells
Solution Approach 2:
The fine TDC is activated only when needed for high-resolution measurements, and the coarse TDC handles routine measurements independently, creating an efficient power management scheme where each component operates autonomously within its optimal range
3Measurement precision
If a plurality of delay cells is used to meet high resolution and wide input frequency range requirements, then measurement precision is improved, but testing robustness decreases due to process variations
Solution Approach 1:
The patent segments the measurement range into coarse and fine portions, allowing the coarse TDC to handle large variations robustly while the fine TDC provides high-resolution measurements within a limited range where process variations have minimal impact
Solution Approach 2:
The coarse TDC acts as an intermediary that handles the bulk of time measurement and compensates for process variations, allowing the fine TDC to operate in a controlled range where high precision can be achieved with reduced sensitivity to manufacturing variations
4Adaptability or versatility
If a unified clock performance circuit is designed to support multiple measurement modes with high resolution and wide frequency range, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal clock measurement interface that can handle multiple measurement modes (period jitter, duty cycle, skew, TIE) through a single unified architecture combining coarse and fine TDCs, eliminating the need for separate dedicated circuits for each measurement type
Solution Approach 2:
By segmenting the measurement function into coarse and fine components, the patent reduces the complexity of each individual component while maintaining overall high resolution, making the unified multi-mode interface more manageable and less complex than a single high-resolution TDC would require
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high accuracy and a wide input frequency range with reduced chip area and power consumption, providing robust and precise clock performance measurements across diverse modes.
Implementation Method 1
a slow oscillator that begins oscillating a slow oscillator output signal responsive to the first clock edge
Implementation Method 2
A coarse counter counts the coarse count responsive to the slow oscillator output signal
Implementation Method 3
A fast oscillator begins oscillating a fast oscillator output signal responsive to the a second clock edge
Implementation Method 4
A fine counter counts the fine count responsive to the fast oscillator output signal
Data Source
AI summary
A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.