Sub-rate Phase Interpolator CDR with Skew Correction
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Solution Overview
Problem
In sub-rate phase-interpolator based CDR architectures, random delay variations can cause phase-skew errors between in-phase (I) and quadrature (Q) clock phases, leading to misalignment of data sampling margins.
Innovation Solution
A skew-correction loop is implemented, comprising skew detection circuitry to generate a skew error signal and skew-correction offset circuitry to produce a correction signal that modifies the PI control signals, ensuring accurate phase alignment and correcting phase-skew errors between PI sub-rate clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sub-rate phase-interpolator based CDR architecture is used to generate multi-phase interpolated clock signals, then data sampling capability is improved, but phase-skew errors between I and Q clock phases occur due to random delay variations
Solution Approach 1:
The patent implements a skew-correction loop that continuously monitors the phase relationship between I and Q clock signals using skew detection circuitry. The detected skew error is fed back through skew-correction offset circuitry that generates correction signals to adjust the phase interpolator control, thereby dynamically compensating for phase-skew errors and maintaining accurate phase alignment despite random delay variations.
Solution Approach 2:
The patent modifies the control parameters of the phase interpolator by introducing a skew-correction offset signal that adjusts the phase relationship between I and Q clocks. This parameter adjustment compensates for random delay variations without changing the fundamental architecture, allowing the system to maintain 1/4 UI phase alignment while operating in sub-rate mode.
2Manufacturing precision
If skew-correction loop is added to correct phase-skew errors, then phase alignment accuracy is improved, but device complexity increases
Solution Approach 1:
The skew-correction loop is nested within the existing CDR architecture, with the skew detection circuitry and skew-correction offset circuitry integrated into the phase interpolator control structure. This nested arrangement allows the correction mechanism to operate within the existing control bandwidth without requiring a completely separate correction system, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent introduces skew-correction offset circuitry as an intermediary component that sits between the skew detection circuitry and the phase interpolator control. This intermediary processes the skew error signal and generates appropriate correction signals, acting as a buffer that isolates the complexity of the correction mechanism from both the detection and control stages.
3Manufacturing precision
If traditional skew correction methods are used, then phase-skew errors are corrected, but power consumption increases and noise is introduced due to modifications in high-speed clock paths
Solution Approach 1:
The patent extracts the skew correction function from the high-speed clock path and implements it in the low-speed control path. The skew detection and correction mechanisms operate on control signals rather than the high-speed clock signals themselves, thereby correcting phase-skew errors without introducing noise or increasing power consumption in the critical high-speed data path.
Solution Approach 2:
The skew-correction offset circuitry serves as an intermediary that translates skew errors into correction signals operating at control bandwidth frequencies. This intermediary approach allows phase alignment correction without directly manipulating the high-speed clock signals, thereby avoiding the introduction of noise and reducing power consumption in the high-speed path.
Data Source
AI summary
A sub-rate (such as half-rate I and Q) phase-interpolator based CDR architecture is configured to receive serial data signals and multiple sub-rate clock signals (such as generated by a VCO either integrated or external). The CDR includes multiple phase interpolators to generate, from respective sub-rate clock signals, respective PI (phase-interpolated) sub-rate clock signals. A CDR loop is configured to receive the input data and the PI sub-rate clock signals, and to generate multiple PI control signals, each to control a respective phase interpolator to align the PI sub-rate clock signals to the data edges. A skew-correction loop includes skew detection circuitry to generate a skew error signal from the PI sub-rate clock signals corresponding to a skew error between the PI sub-rate clock signals, and skew-correction offset circuitry to generate, from the skew error signal, a skew-correction offset signal to modify a selected PI control signal.