Subroutine Cache Control Logic for Stall-Free Processor Calls
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Solution Overview
Problem
The repeated execution of subroutines in computer processors leads to increased energy consumption and processor performance degradation due to memory access and pipeline stalls during subroutine call and return instructions.
Innovation Solution
A processor with a subroutine cache that includes instruction storage, a subroutine address register, and control logic to manage subroutine validity, allowing direct access to cached subroutines without pipeline stalls, reducing energy consumption and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If subroutines are executed repeatedly by reading from instruction memory, then program organization is improved, but energy consumption increases
Solution Approach 1:
The patent implements a subroutine cache that pre-stores frequently executed subroutine instructions in a dedicated cache memory structure. When a subroutine is called, the instructions are already available in the cache, eliminating the need to repeatedly fetch them from main instruction memory. This preliminary action of caching resolves the contradiction by maintaining good program organization through subroutine reuse while dramatically reducing energy consumption from memory access operations.
2Device complexity
If subroutines are executed by fetching from instruction memory, then program size is reduced, but processor performance deteriorates due to pipeline stalls
Solution Approach 1:
The subroutine cache pre-loads and stores subroutine instructions in a dedicated cache structure before they are needed for execution. This preliminary action ensures that when subroutines are called, the instructions are already available in the cache, preventing pipeline stalls and maintaining high processor performance while still allowing compact program organization through subroutine reuse.
Solution Approach 2:
The patent introduces a subroutine cache as an intermediary structure between the instruction memory and the execution unit. This intermediary cache buffer resolves the contradiction by decoupling the compact program structure from the performance-critical instruction fetch operation, allowing the processor to execute subroutines at full speed without being bottlenecked by memory access delays.
3Device complexity
If subroutine instructions are fetched from instruction memory each time, then memory access is simplified, but execution speed decreases due to repeated access
Solution Approach 1:
The subroutine cache pre-stores subroutine instructions in a dedicated cache memory, performing the memory access preparation in advance. This preliminary action resolves the contradiction by maintaining simple memory access operations while dramatically increasing execution speed, as the cached instructions are available immediately without requiring repeated accesses to the main instruction memory.
Data Source
AI summary
A processor includes an execution unit and a subroutine cache. The execution unit is configured to execute instructions. The subroutine cache us configured to provide instructions of a subroutine to the execution unit for execution. The subroutine cache includes subroutine instruction storage, a subroutine address register, and subroutine cache control logic. The subroutine control logic is configured to: identify a subroutine call instruction provided to the execution unit; determine whether an instruction of a subroutine invoked by the subroutine call instruction is stored in the subroutine instruction storage by evaluating a subroutine validity indicator that indicates whether at least a portion of the subroutine is stored in the subroutine instruction storage; and provide the instruction of the subroutine to the execution unit based on the subroutine validity indicator indicating that at least a portion of the subroutine is stored in the subroutine instruction storage.