DAC Feedback Loop with Sub-Sampled ADC for Nonlinearity Training
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Solution Overview
Problem
Digital-to-analog conversion systems face challenges in mitigating nonlinearity, leading to harmonic and inter-modulation distortions, which introduce interference in communication channels, and existing Digital Pre-Distortion (DPD) techniques require complex and costly high-speed ADCs for training.
Innovation Solution
A digital-to-analog conversion system with a sub-sampled ADC feedback loop, allowing for reduced complexity, size, and cost by using a Successive Approximation Register (SAR) ADC or other types of ADCs with lower sample rates, enabling effective DPD training without the need for high-speed/full-speed ADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-speed ADCs are used for DPD training, then measurement precision and reliability are improved, but device complexity and cost increase
Solution Approach 1:
The system separates the ADC functionality into two distinct roles: a full-speed ADC dedicated to DPD training and characterization, and a sub-sampled ADC for routine feedback operations. This segmentation allows each ADC to be optimized for its specific function, with the full-speed ADC being smaller and less complex since it only needs to operate at high speed during training periods rather than continuously.
Solution Approach 2:
The system performs DPD training and ADC characterization in advance using the full-speed ADC before normal operation begins. By completing the complex measurement and training tasks beforehand, the system establishes accurate distortion models and compensation parameters that can then be used during normal operation with the simpler sub-sampled ADC feedback loop.
2Measurement precision
If full-speed ADCs are used continuously, then measurement precision is maintained, but power consumption increases
Solution Approach 1:
The system dynamically switches between two ADC operating modes: during DPD training phases, the full-speed ADC is activated to capture accurate feedback signals for model development; during normal operation, the system transitions to using the sub-sampled ADC which consumes significantly less power while maintaining sufficient accuracy for routine feedback control.
Solution Approach 2:
The system extracts the high-power full-speed ADC from the continuous operation path and uses it only during periodic training and characterization intervals. The sub-sampled ADC handles continuous feedback operations, effectively removing the power consumption burden of high-speed conversion from the steady-state operational profile.
3Device complexity
If sub-sampled ADCs are used, then device complexity and power consumption are reduced, but measurement precision may deteriorate
Solution Approach 1:
The full-speed ADC acts as an intermediary calibration tool that characterizes the sub-sampled ADC's performance and distortion behavior. By measuring the sub-sampled ADC's output with the high-precision full-speed ADC during training, the system creates correction models that compensate for the sub-sampled ADC's limitations, effectively mediating between the low-cost sensor and the accuracy requirements.
Solution Approach 2:
The system changes the operational parameters of the sub-sampled ADC based on training data collected by the full-speed ADC. By adjusting sampling rates, trigger levels, and conversion timing based on characterized distortion patterns, the system optimizes the sub-sampled ADC's performance for specific operating conditions, maintaining measurement adequacy despite reduced sampling frequency.
Data Source
AI summary
A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.