Sub-Sampled ADC Feedback in DACs for Nonlinearity Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital-to-analog conversion systems face challenges in mitigating nonlinearity, leading to harmonic and inter-modulation distortions, which introduce interference in communication channels, and existing Digital Pre-Distortion (DPD) techniques require complex and costly high-speed ADCs for training.
Innovation Solution
A digital-to-analog conversion system with a sub-sampled ADC feedback loop that allows for reduced complexity, size, and cost by using a Successive Approximation Register (SAR) or other types of ADCs with lower sample rates, enabling effective DPD training without the need for high-speed/full-speed ADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-speed/full-speed ADCs are used for DPD training, then measurement precision and reliability are improved, but device complexity, size, and cost increase
Solution Approach 1:
The feedback loop is segmented into multiple stages: a full-speed ADC captures high-frequency signal characteristics for DPD training, while a sub-sampled ADC handles continuous monitoring at lower speeds. This segmentation allows the system to obtain precise training data without requiring the entire feedback path to operate at full speed, thereby reducing overall complexity and power consumption while maintaining DPD accuracy.
Solution Approach 2:
The system employs periodic full-speed sampling interspersed with sub-sampled monitoring. During periodic DPD training intervals, the full-speed ADC operates to capture accurate signal characteristics, while between these intervals, the sub-sampled ADC performs lower-rate monitoring. This periodic action pattern allows high-precision measurement only when necessary for training, reducing average complexity and power consumption while maintaining measurement precision when needed.
2Measurement precision
If full-speed ADCs are used for feedback, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The ADC sampling rate is made dynamic rather than static. The system switches between full-speed operation during DPD training phases and sub-sampled operation during normal operation. This dynamic adjustment of the sampling rate allows the system to achieve high measurement precision when needed for training while consuming significantly less power during continuous operation, directly resolving the contradiction between precision and power consumption.
Solution Approach 2:
The sampling rate parameter of the ADC is changed based on operational requirements. During DPD training, the sampling rate is set to the full speed to ensure measurement precision. During normal operation, the sampling rate is reduced to sub-sampled levels to minimize power consumption. This parameter change strategy allows the system to optimize the trade-off between measurement precision and power consumption根据不同 operational phases.
3Device complexity
If sub-sampled ADCs are used, then device complexity and power consumption are reduced, but measurement precision may deteriorate
Solution Approach 1:
The measurement function is segmented between two ADCs with different sampling rates. The sub-sampled ADC provides continuous monitoring with reduced complexity, while the full-speed ADC periodically captures high-precision signal characteristics needed for DPD training. This segmentation allows the system to use simple sub-sampled operation for most purposes while maintaining high measurement precision when required for training accuracy.
Solution Approach 2:
The system creates a simplified copy of the feedback path using the sub-sampled ADC for continuous monitoring, while the full-speed ADC periodically captures complete signal information for training. The sub-sampled version serves as a low-complexity approximation that suffices for ongoing operation, while the full-speed copy is used specifically for training purposes where high precision is critical, thus resolving the contradiction between simplicity and accuracy.
Data Source
AI summary
A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.