Sub-Sampling Frequency Detector for Low-Power Oscillator Tuning
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Solution Overview
Problem
Ultra-low power wireless communication devices, such as wake-up receivers, face challenges with high power consumption and limited immunity to interference due to the use of amplitude detection and limited filtering, which makes them vulnerable to adjacent channel interference.
Innovation Solution
A frequency detection and generation circuitry that employs sub-sampling of controlled oscillator states using multiple low-frequency sampling pulses, eliminating the need for power-hungry PLLs and frequency dividers, and utilizing a digital processing unit to calculate frequency offsets and generate control signals for accurate tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If amplitude detection is used in wake-up receivers to achieve ultra-low power consumption, then power consumption is reduced, but immunity to interference deteriorates
Solution Approach 1:
The patent replaces the conventional amplitude detection mechanism with a frequency detection mechanism. Instead of detecting signal amplitude directly, the system uses a controlled oscillator tuned to the expected signal frequency, samples its output states at multiple low-frequency sampling rates, and digitally processes the sampled states to determine frequency offset. This substitution enables effective filtering of adjacent channel interference while maintaining ultra-low power consumption below 100 uW.
2Object-affected harmful factors
If more filtering is applied prior to amplitude detection to improve immunity to interference, then immunity to interference is improved, but power consumption increases
Solution Approach 1:
The patent substitutes the filtering-and-amplitude-detection approach with a frequency-based sampling approach. By using a controlled oscillator and sampling its output states at multiple low sampling frequencies, the system achieves effective frequency selectivity without requiring power-hungry filtering circuits. The digital processing of sampled states provides the necessary interference rejection while keeping power consumption ultra-low.
3Measurement precision
If phase-locked loops (PLLs) are used for frequency generation to achieve high frequency accuracy, then frequency accuracy is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic sampling action instead of continuous PLL operation. The system samples the controlled oscillator output states at multiple discrete low-frequency sampling rates periodically, rather than using a continuous high-power PLL. This periodic sampling approach achieves the necessary frequency measurement accuracy while consuming significantly less power, as the sampling circuitry operates only at low frequencies and is activated periodically for frequency detection and tuning.
Data Source
AI summary
A frequency detector (200) and method therein for measuring and tuning a frequency of a controlled oscillator are disclosed. The frequency detector (200) comprises a pulse generator (210) for generating sampling pulses; a sample circuitry (220) for sampling output states of the controlled oscillator (180); and a digital processing unit (230). The sample circuitry (220) is configured to sub-sample the output states of the controlled oscillator (180) at two or more sampling frequencies, and all sampling frequencies are lower than the frequency of the controlled oscillator. The digital processing unit (230) is configured to calculate a frequency offset of the oscillator based on the sampled states and generate a control signal based on the frequency offset to tune the frequency of the oscillator.