Low-Offset Subsampling Phase Detector With Regulated Current Mirror
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Solution Overview
Problem
Subsampling phase detectors often exhibit nonzero offset due to P-N mismatch between current sources and sinks, leading to reduced detection range and inaccurate phase alignment, especially at high frequencies.
Innovation Solution
A subsampling phase detector design incorporating a pulse generator, sampling network, V2I converter, regulated current mirror, current steering networks, and a lowpass filter, with a unity-gain buffer to maintain stable DC conditions and minimize offset, utilizing a closed-loop current mirroring and programmable delay to adjust gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a subsampling phase detector uses conventional current sources and sinks, then the device can operate at high frequencies, but P-N mismatch between current sources and sinks causes nonzero offset that reduces detection range and accuracy
Solution Approach 1:
The patent changes the operating parameters of the current mirror by introducing a regulated standby voltage that dynamically adjusts the mirror ratio. This allows the current mirror to maintain accurate current matching despite process variations and P-N mismatches, thereby reducing offset and improving phase detection accuracy while maintaining high-frequency operation
Solution Approach 2:
The patent implements a feedback mechanism where a buffer amplifier continuously monitors the standby node voltage and adjusts the current mirror operation accordingly. This closed-loop feedback ensures that the current sources and sinks remain balanced, compensating for P-N mismatch and minimizing offset errors in the phase detector
2Speed
If a subsampling phase detector operates in pulsed manner, then it can achieve high frequency operation, but it becomes difficult to maintain stable DC conditions which increases offset
Solution Approach 1:
The patent establishes stable DC conditions beforehand by creating a regulated standby voltage that is maintained throughout the pulsed operation. This preliminary establishment of stable bias conditions ensures that when the phase detector operates in pulsed manner at high frequencies, the DC operating points remain stable and offset is minimized
Solution Approach 2:
The patent introduces a standby voltage as an intermediary element that mediates between the pulsed operation and DC stability requirements. This standby voltage acts as a buffer that maintains stable DC conditions during pulsed operation, allowing high-frequency operation without sacrificing DC stability
3Device complexity
If current mirror ratio is fixed, then the circuit is simpler, but it cannot compensate for P-N mismatch and process variations leading to higher offset
Solution Approach 1:
The patent transitions from a fixed current mirror ratio to a dynamic, regulated current mirror ratio. The standby voltage dynamically adjusts the effective mirror ratio to compensate for P-N mismatch and process variations, improving phase detection accuracy while adding only moderate circuit complexity through the buffer amplifier and regulation network
Data Source
AI summary
A method of phase detection includes receiving a reference clock and an input clock having a first input signal and a second input; sampling the first input signal and the second input signal into a first sample and a second sample; converting the first sample and the second sample into a first current and a second current; using a regulated current mirror to convert the first current into the third current; using a first current steering network to steer the second current into either a fourth current or a fifth current in accordance with a pulse signal; using a second current steering network to steer the third current into either a sixth current or a seventh current; connecting a lowpass filter to the output node to establish an output voltage and a lowpass-filtered voltage; and forcing the standby voltage to be equal to the lowpass-filtered voltage using a unity-gain buffer.