Sub-Sampling PLL Buffer Compensation for Stable Loop Bandwidth

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Solution Overview

Problem

Phase-locked loop (PLL) circuits are vulnerable to process, voltage, and temperature (PVT) changes, which affect the loop bandwidth and lead to noise characteristics that deteriorate the performance of clock generators, particularly in sub-sampling PLL circuits used for phase-locking operations.

Innovation Solution

Incorporating a replica buffer and a pulse generator within the sub-sampling PLL circuit to detect changes in buffer characteristics due to PVT variations, generating a comparative voltage signal, and adaptively adjusting the pulse width of internal signals to maintain a constant loop bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a buffer circuit is used in the sub-sampling PLL circuit to prevent instantaneous phase distortion, then the phase locking performance is improved, but the loop bandwidth changes due to PVT variations

Engineering Contradiction:

Improvephase locking performanceVSAvoidloop bandwidth stability

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent uses a replica buffer that copies the characteristics of the main buffer circuit. The replica buffer experiences the same PVT variations but is used only for detection purposes. By monitoring the replica buffer's characteristics, the system can detect PVT changes and compensate for them, maintaining stable loop bandwidth while allowing the main buffer to provide reliable phase locking.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent implements a feedback mechanism where the characteristic detector continuously monitors the buffer's characteristics and feeds this information back to the pulse generator. The pulse generator then adjusts the pulse width based on this feedback to compensate for PVT variations, maintaining constant loop bandwidth despite changes in the buffer circuit characteristics.

Inventive Principle:

Principle #23Feedback

2Object-affected harmful factors

If the loop bandwidth is widened to improve noise characteristics, then the noise performance is improved, but the phase locking stability deteriorates

Engineering Contradiction:

Improvenoise characteristicsVSAvoidphase locking stability

Core Design Contradiction:

Object-affected harmful factorsVSStability of the object's composition

Solution Approach 1:

The patent dynamically adjusts the loop bandwidth based on operating conditions. By using the replica buffer to detect PVT changes and adjusting the pulse width accordingly, the system can optimize the loop bandwidth for different conditions - wider bandwidth for improved noise characteristics when needed, and narrower bandwidth for enhanced phase locking stability when required.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20210021273A1Phase-locked loop (PLL) circuit and clock generator including sub-sampling circuit

Publication Date: 2021.01.21 SAMSUNG ELECTRONICS CO LTD

AI summary

A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock, and a sub-sampling PLL circuit configured to receive, from the voltage-controlled oscillator, the generated output clock as feedback, and perform a phase-locking operation on the received output clock. The sub-sampling PLL circuit includes a buffer configured to buffer the received output clock, and the sub-sampling PLL circuit is further configured to adaptively adjust an internal signal to maintain a loop bandwidth of the sub-sampling PLL circuit, based on a change of a characteristic of the buffer according to at least one of process, voltage, and temperature (PVT) change.