Subsampling PLL with DTC-SAR Phase Estimation for Fast Locking
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Solution Overview
Problem
Conventional phase-locked loop (PLL) based frequency synthesizers in RF communication devices face challenges with long settling time and high power consumption, especially when the frequency of the output signal is at a GHz-level and the reference signal frequency is much lower, leading to inefficient frequency division.
Innovation Solution
A digital subsampling PLL with a digital-to-time converter (DTC) based successive-approximation-register (SAR) phase estimation, which includes a phase sampling unit, a SAR phase estimator, and a digitally controlled oscillator (DCO), using a sampling clock offset by a time delay from the reference signal, updated in each clock-cycle, to reduce settling time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a frequency divider is used to reduce the frequency of the LO output signal in the feedback loop, then the frequency can be reduced from GHz-level to reference signal level, but the frequency divider becomes a high-power consumption component
Solution Approach 1:
The patent extracts the frequency division function from the conventional feedback loop and replaces it with a digital subsampling architecture. The phase sampling unit samples the LO output signal at a lower rate, effectively removing the need for a high-frequency frequency divider and thereby reducing its power consumption while maintaining the frequency synthesis function.
Solution Approach 2:
The patent replaces the conventional analog frequency divider with a digital subsampling approach using a phase sampling unit and digital signal processing. This substitution transitions from a high-frequency analog division mechanism to a lower-frequency digital sampling system, reducing power consumption while achieving the same frequency synthesis objective.
2Loss of time
If the phase of the divided RF signal is adjusted to align with the reference signal phase, then signal alignment is achieved, but the settling time becomes long
Solution Approach 1:
The patent implements preliminary phase sampling and estimation before final phase locking. The phase sampling unit performs initial phase measurements and the SAR phase estimator generates preliminary phase words that guide the DCO. This preliminary action reduces the time required for final phase alignment while maintaining precision through the iterative SAR algorithm.
Solution Approach 2:
The patent employs a feedback mechanism where the phase sampling unit continuously monitors the LO output signal phase, the SAR phase estimator processes this information to generate phase correction words, and the DCO adjusts its output based on this feedback. This closed-loop feedback system achieves rapid and precise phase alignment by continuously correcting phase errors.
Data Source
AI summary
The present disclosure relates to a digital subsampling phase-locked-loop (PLL) with a digital-to-time converter (DTC) based successive-approximation-register (SAR) phase estimation. This disclosed PLL utilizes a DTC and a one-bit sampler to generate one phase word by calculating multiple one-bit phase measurements with a SAR algorithm. The one phase word, which indicates the phase estimation of a radio frequency (RF) output signal compared to a reference signal, enables the PLL to lock the RF output signal with the reference signal in a short settling time. In addition, utilizing the one-bit sampler instead of a conventional frequency divider is good for linearity and low power consumption of the PLL without introducing significant noise in the RF output signal.