Sub-Sampling PLL Clock Generator With DLL-Based Fractional Division
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Solution Overview
Problem
Existing phase-locked loops (PLLs) with fractional frequency division-based phase locking suffer from limited resolution and increased quantization noise, particularly in sub-sampling operations, which degrades the performance of clock generators.
Innovation Solution
A PLL circuit incorporating a fractional frequency division control circuit with a voltage-controlled delay line, replica voltage-controlled delay line, and digital-to-time converter to generate a selection reference clock signal, enhancing resolution and reducing quantization noise by adjusting delay times and frequencies for precise phase locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a digital-to-time converter is used to enable fractional frequency division operation during sub-sampling, then the operation becomes possible, but the clock generator performance is degraded due to limited resolution and quantization noise
Solution Approach 1:
A delay-locked loop (DLL) is introduced as an intermediary component between the phase detector and the digital-to-time converter. The DLL processes the feedback signal through voltage-controlled delay lines to generate delay information, which is then used to control the DTC. This intermediary processing improves the resolution of the fractional frequency division operation by providing more precise delay control, thereby reducing quantization noise while maintaining the operational capability.
2Adaptability or versatility
If a divider is used in the feedback path for fractional frequency division, then frequency division is achieved, but the divider does not perform frequency division on a clock during sub-sampling operation, limiting performance
Solution Approach 1:
The traditional divider-based frequency division mechanism is replaced with a delay-locked loop system that uses voltage-controlled delay lines and digital-to-time conversion. Instead of using a divider circuit that cannot operate during sub-sampling, the invention uses a DLL-based approach where delay information is extracted from the feedback signal and used to control the timing of reference clock signals. This substitution enables fractional frequency division to function properly during sub-sampling operations, significantly improving performance.
Data Source
AI summary
A phase-locked loop (PLL) circuit may include a voltage-controlled oscillator, a sub-sampling PLL circuit, and a fractional frequency division control circuit. The fractional frequency division control circuit may include a voltage-controlled delay line that routes a feedback signal to generate delay information, a replica voltage-controlled delay line to which the delay information is applied and configured to route a reference clock signal to generate a plurality of delay reference clock signals each delayed by up to a different respective delay time, and a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.