Subsampling Phase Detector for Divider-Less PLL Harmonic Locking

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Solution Overview

Problem

Conventional phase-locked loops (PLLs) suffer from noise performance limitations, power consumption, and area requirements due to the presence of frequency dividers, which increase noise contributions and create harmonic-locking issues.

Innovation Solution

A divider-less PLL design utilizing a subsampling phase and frequency detector (SSPFD) that measures duty cycles to determine frequency and phase relationships between reference and voltage-controlled oscillator signals, eliminating the need for dividers and addressing harmonic-locking problems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a frequency divider is used in the feedback loop, then the PLL can achieve frequency alignment, but noise contributions increase by approximately 20*log(M) dB and divider noise is multiplied by M² at the output

Engineering Contradiction:

Improvefrequency alignment precisionVSAvoidnoise performance

Core Design Contradiction:

Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent removes the frequency divider from the feedback loop entirely, extracting the noise-generating component while preserving the frequency alignment function through an alternative mechanism (phase detector comparing VCO output directly with reference signal or its harmonics). This eliminates the 20*log(M) dB noise contribution and M² noise multiplication effects.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the operating parameters by using harmonic relationships (multiples of reference frequency) instead of direct division. The phase detector compares the VCO output frequency with integer multiples of the reference frequency, allowing frequency locking without the noisy division operation.

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If a frequency divider with large division factor is used, then frequency alignment is achieved, but power consumption and area requirements increase

Engineering Contradiction:

Improvefrequency alignment precisionVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent extracts and removes the frequency divider circuitry from the system, eliminating the power consumption and area requirements associated with large division factors. The frequency alignment function is achieved through a simpler phase comparison mechanism.

Inventive Principle:

Principle #2Taking out (Extraction)

3Measurement precision

If a frequency divider is used in the feedback loop, then frequency alignment is achieved, but the PLL suffers from harmonic-locking issues

Engineering Contradiction:

Improvefrequency alignment precisionVSAvoidlocking range and stability

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The patent converts the potential harm of harmonic relationships into a benefit by deliberately using harmonic comparison. The phase detector is designed to compare VCO frequency with integer multiples of reference frequency, turning what could be a source of ambiguity (harmonic-locking issues) into a reliable frequency multiplication capability.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution improves noise performance, reduces power consumption, and extends the frequency-locking range by eliminating divider noise and harmonic-locking issues, while being applicable to both analog and digital PLLs.

Implementation Method 1

uses a first edge of the reference signal, which is either a rising or falling edge, to clock the VCO-output signal into a first D-flip-flop (D-FF)

Methodology Applied

Scientific EffectSampling:

Implementation Method 2

uses a second edge of the reference signal, which is opposite the first edge, to clock the output of the first D-FF into a second D-FF

Methodology Applied

Scientific EffectSampling:

Implementation Method 3

exclusive-ORs the output of the first D-FF with the output of the second D-FF to generate a PR signal

Methodology Applied

Scientific EffectExclusive-OR logic operation:

Implementation Method 4

performs a duty-cycle measurement on the PR signal to measure the first duty cycle

Methodology Applied

Scientific EffectDuty cycle measurement:

Data Source

PatentUS10425092B2Subsampling phase frequency detector for a divider-less phase-locked loop

Publication Date: 2019.09.24 ORACLE INT CORP

AI summary

The disclosed embodiments relate to a system that controls a phase-locked loop (PLL), eliminating harmonic locking issues during subsampling operation and achieving better noise performance. During operation, the system performs a procedure to measure a first duty cycle that indicates a relationship between a reference signal, which has a frequency FREF, and a voltage-controlled oscillator (VCO) output signal, which has a frequency FVCO and is generated by a VCO. The system also performs the procedure to measure a second duty cycle that indicates a relationship between a second reference signal (with a frequency of c*FREF) and the VCO-output signal. Next, the system determines a frequency and phase relationship between the reference signal and the VCO-output signal based on the first and second duty cycles. Finally, the system uses the frequency and phase relationship to adjust the VCO so that the VCO-output signal, which is used as an output of the PLL, is frequency and phase aligned with the reference signal.