Sub-Sampling PLL Phase Detector Without a Frequency Divider
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Solution Overview
Problem
Existing phase-locked loop (PLL) systems, particularly millimeter-wave PLLs, face challenges in maintaining low phase noise and signal-to-noise ratio (SNR) due to limitations in phase detection techniques, especially with the presence of frequency dividers, which contribute to high in-band phase noise and jitter.
Innovation Solution
The implementation of a sub-sampling phase detector (SSPD) with a switched emitter-follower (SEF) sampling network, which operates up to higher frequencies than CMOS samplers and is compatible with BiCMOS processes, eliminates the frequency divider and reduces in-band phase noise by directly comparing the VCO output with the reference input, thereby improving SNR and reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a frequency divider is used in the PLL system, then the phase detection can be performed, but the in-band phase noise and jitter increase
Solution Approach 1:
The patent removes the frequency divider from the PLL system and replaces it with a sub-sampling phase detector that directly compares the VCO output with the reference input. This extraction of the harmful frequency divider element eliminates its noise contributions while maintaining phase detection functionality through direct comparison of the oscillating signals.
Solution Approach 2:
The sub-sampling phase detector acts as an intermediary that enables phase detection without requiring a frequency divider. It directly compares the phase of the VCO output with the reference input, mediating the phase detection function while avoiding the noise-generating mechanism of traditional frequency dividers.
2Reliability
If a traditional phase detector is used, then the phase lock can be maintained, but the device complexity increases due to additional components
Solution Approach 1:
The patent merges the phase detection function directly into the sampling network, eliminating the need for separate frequency dividers and traditional phase detectors. The sub-sampling phase detector combines multiple functions into a single integrated structure, reducing device complexity while maintaining phase lock stability.
Solution Approach 2:
The sub-sampling phase detector serves multiple functions: it performs phase detection, frequency comparison, and signal sampling simultaneously. This multi-functional approach replaces what would traditionally require multiple separate components, thereby reducing overall system complexity while maintaining reliable phase locking.
3Ease of manufacture
If CMOS samplers are used, then the circuit can be implemented, but the operating frequency is limited
Solution Approach 1:
The patent changes the sampling methodology from direct CMOS sampling to sub-sampling techniques that can operate at higher frequencies. By using a switched emitter-follower sampling network with careful timing and clock frequency selection (where the sampling frequency is a sub-multiple of the VCO frequency), the system achieves millimeter-wave operation while maintaining compatibility with standard semiconductor processes.
Data Source
AI summary
Techniques are disclosed for phase detection in a phase-locked loop (PLL) control system, such as a millimeter-wave PLL. A PLL control system includes a voltage-controlled oscillator (VCO) circuit and a sub-sampling phase detector (SSPD). The VCO circuit is configured to generate an oscillating VCO output voltage based at least in part on an error signal generated by the SSPD. The error signal is proportional to a phase difference between an oscillating reference input voltage and the oscillating VCO output voltage. The SSPD includes a switched emitter-follower (SEF) sampling network, also referred to in this disclosure as an SEF circuit. In contrast to existing CMOS-based techniques, the SEF sampling network allows the SSPD to operate up to higher frequencies, for example, greater than 100 GHz, than possible using a CMOS sampler, and is also compatible with BiCMOS processes, which generally do not have access to advanced small-geometry CMOS.