Sub-Sampling PLL Interpolation for Lower Phase Noise
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Solution Overview
Problem
Conventional sub-sampling phase-locked loops face limitations due to the limited resolution of digital-to-time converters, leading to spectral degradation and increased phase noise and spurious tones in PLL outputs.
Innovation Solution
The implementation of a sub-sampling phase-locked loop with a digital-to-time converter providing two delay signals and a sampler module that captures samples at different points in time, with an interpolator generating a sampler signal by interpolating these samples to control the voltage-controlled oscillator, effectively increasing spectral purity without enhancing DTC resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the digital-to-time converter is increased, then the spectral purity of the PLL output is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the sampling process into multiple segments by taking multiple samples at different time points (first sample at time t1, second sample at time t2, etc.) instead of relying on a single high-resolution DTC. Each sample is processed separately and then combined through interpolation to achieve the equivalent effect of higher DTC resolution without increasing DTC complexity
Solution Approach 2:
The patent introduces an interpolator as an intermediary component that processes the multiple lower-resolution samples to generate an interpolated sampler signal. This interpolator acts as a mediator between the limited-resolution DTC and the VCO, effectively recovering the spectral purity that would otherwise require a much higher resolution DTC
2Measurement precision
If multiple samples are taken and interpolated, then the spectral degradation is reduced, but the device complexity increases due to additional components
Solution Approach 1:
The sampling function is segmented across multiple time points with each sampler instance handling a specific time point. Instead of one complex high-resolution sampler, multiple simpler samplers operate in parallel at different delays, dividing the complex sampling task into manageable segments
Solution Approach 2:
The system uses periodic sampling at multiple fixed time points (t1, t2, etc.) with regular intervals. This periodic multi-point sampling approach replaces the need for continuous high-resolution sampling, achieving accurate phase detection through discrete periodic measurements that are then interpolated
3Ease of manufacture
If the DTC delay resolution is limited, then the implementation is simpler, but spurious tones and phase noise increase
Solution Approach 1:
The patent converts the harmful quantization error from limited DTC resolution into a useful signal structure. The deterministic ramp-like shape of the DTC delay creates predictable sampling points that, when multiple samples are taken and interpolated, actually provide rich information that can be processed to eliminate spurious tones. The limitation becomes a structured pattern that interpolation can exploit rather than a source of noise
Solution Approach 2:
The system uses feedback through the loop filter and VCO to continuously adjust and correct the phase errors introduced by limited DTC resolution. The interpolated sampler signal provides feedback information that drives the VCO adjustments, progressively reducing spurious tones and phase noise in the output
Data Source
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AI summary
A sub-sampling phase-locked loop (100) is described, which comprises a digital-to-time converter (102), a sampler module (104), an interpolator (106), and a voltage controlled oscillator (108). The digital-to-time converter (102) is configured to provide a first delay signal SDLY1 at a first point t1 in time and a second delay signal SDLY2 at a second point in time t2. The sampler module (104) is configured to provide a first sample S1 of the oscillator output signal SOUT at the first point in time t1 and a second sample S2 of the oscillator output signal SOUT at the second point in time t2. The interpolator (106) is configured to provide a sampler signal SSAMPL by interpolating the first sample S1 and the second sample S2. The voltage controlled oscillator (108) is configured to control the oscillator output signal SOUT based on the sampler signal SSAMPL.