Sub-Sampling PLL Bandwidth Compensation for PVT Variation
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in maintaining consistent loop bandwidth due to process, voltage, and temperature (PVT) variations, leading to performance issues in synchronizing clock signals between processors and peripheral devices.
Innovation Solution
A sub-sampling phase locked loop (PLL) is designed with a slope generating and sampling circuit, transconductance circuits, a constant transconductance bias circuit, and a voltage controlled oscillator, incorporating a switched capacitor resistor to compensate for PVT variations by canceling the influence of resistor and capacitor distributions on loop bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL designs are used, then the circuit structure is simple, but the loop bandwidth is sensitive to PVT variations
Solution Approach 1:
The patent introduces a switched capacitor resistor as an intermediary component that mediates between the PVT variations and the loop bandwidth. This SCR acts as a compensating element that counteracts the effects of resistor and capacitor distribution variations, thereby stabilizing the loop bandwidth without requiring a complete redesign of the PLL architecture.
Solution Approach 2:
The patent changes the parameter of resistance by using a switched capacitor resistor instead of a conventional resistor. This parameter change allows the circuit to compensate for PVT variations dynamically. The equivalent resistance of the SCR can be adjusted through switching operations, enabling compensation for the effects of temperature and process variations on the loop bandwidth.
2Measurement precision
If resistor and capacitor values are increased to improve timing precision, then the loop bandwidth becomes more sensitive to PVT variations
Solution Approach 1:
The switched capacitor resistor serves as a compensating intermediary that counteracts the increased sensitivity to PVT variations. By introducing this element, the patent creates a balancing mechanism where the SCR's variable resistance compensates for the heightened sensitivity caused by larger resistor and capacitor values, thereby maintaining both timing precision and loop bandwidth consistency.
Solution Approach 2:
The patent implements a feedback mechanism through the switched capacitor resistor that continuously compensates for PVT variations. The SCR is configured to provide compensating current that counteracts the effects of temperature and process variations, creating a feedback loop that maintains stable timing precision and loop bandwidth despite environmental changes.
3Speed
If the PLL is designed for high speed operation, then the loop bandwidth must be precise, but PVT variations cause bandwidth drift
Solution Approach 1:
The patent changes the resistance parameter dynamically using a switched capacitor resistor to compensate for PVT variations. This allows the PLL to maintain precise loop bandwidth at high operating speeds by adjusting the effective resistance to counteract temperature and process drift, enabling high-speed operation without sacrificing bandwidth precision.
Solution Approach 2:
The patent introduces dynamic compensation through the switched capacitor resistor, which can change its equivalent resistance based on operating conditions. This dynamic element allows the PLL to adapt to PVT variations in real-time, maintaining precise loop bandwidth control at high operating speeds where static resistor values would be insufficient.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a loop bandwidth that is relatively insensitive to PVT variations, enhancing the performance and stability of clock signal synchronization in digital systems.
Implementation Method 1
The constant transconductance bias circuit includes a switched capacitor resistor (SCR). The constant transconductance bias circuit is configured to generate the control current.
Data Source
AI summary
A sub-sampling phase locked loop includes a slope generating and sampling circuit, first and second transconductance circuits, a constant transconductance bias circuit, a loop filter and a voltage controlled oscillator. The slope generating and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first and second transconductance circuits generate first and second output control voltages based on the sampling voltage, a reference voltage and a control current. The constant transconductance bias circuit includes a switched capacitor resistor. The constant transconductance bias circuit is configured to generate the control current. The loop filter is connected to output terminals of the first and second transconductance circuits. The voltage controlled oscillator generates the output clock signal based on the first and second output control voltages.