Sub-Sampling PLL with FLL for Wide Millimeter-Wave Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Phase locked loops (PLLs) face challenges in locking onto millimeter-wave frequencies due to high noise and increased power consumption, and sub-sampling PLLs have limited frequency acquisition range, requiring additional power-hungry clock dividers.
Innovation Solution
A sub-sampling phase locked loop (SSPLL) system with a frequency locking loop (FLL) that uses a low frequency alias signal to facilitate wideband frequency tracking without a dedicated frequency divider, reducing power consumption and enabling operation across phase/frequency errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional PLL is used to lock onto millimeter-wave frequencies, then frequency locking capability is provided, but noise increases and power consumption increases
Solution Approach 1:
The system divides frequency tracking into two segments: a frequency locking loop (FLL) for coarse frequency acquisition and a phase locking loop (PLL) for fine frequency tracking. This segmentation allows the FLL to handle large frequency errors with lower power consumption, while the PLL operates only when frequency error is within a smaller range, reducing overall power consumption while maintaining frequency locking capability.
Solution Approach 2:
The system dynamically switches between FLL and PLL operations based on the frequency error magnitude. When frequency error exceeds a threshold, the FLL is activated to rapidly reduce the error; when the error is within the threshold, the PLL operates to maintain precise frequency locking. This dynamic operation adapts to different operating conditions and optimizes power consumption.
2Use of energy by moving object
If a sub-sampling PLL is used to reduce power consumption, then power consumption decreases, but frequency acquisition range is limited
Solution Approach 1:
The system merges the frequency locking loop (FLL) and phase locking loop (PLL) into a unified frequency-acquisition PLL structure. The FLL provides wide frequency acquisition capability by detecting frequency errors directly, while the sub-sampling PLL provides low-power operation for fine frequency tracking. The combination of these two loops achieves both wide frequency acquisition range and reduced power consumption.
Solution Approach 2:
The FLL acts as an intermediary between the wide frequency range requirement and the sub-sampling PLL's limited acquisition range. The FLL first reduces large frequency errors to within the sub-sampling PLL's acquisition range, enabling the PLL to then take over for precise, low-power frequency tracking. This intermediary approach extends the overall frequency acquisition range without sacrificing power efficiency.
3Adaptability or versatility
If clock dividers are added to expand frequency acquisition range, then frequency acquisition range increases, but device complexity increases and power consumption increases
Solution Approach 1:
The invention extracts the frequency division function from the main signal path and implements it digitally in the FLL portion of the system. By using digital frequency division and counter-based frequency detection in the FLL, the system achieves wide frequency acquisition capability without requiring additional high-frequency analog clock dividers in the PLL path, thereby reducing circuit complexity while expanding frequency acquisition range.
Data Source
AI summary
A sub-sampler phase locked loop (SSPLL) system having a frequency locking loop (FLL) and a phase locked loop (PLL) is disclosed. The FLL is configured to detect frequency variations between a phase locked loop (PLL) output signal and a reference frequency and automatically generate a pulsed correction signal upon the detected frequency variations and apply the pulsed correction signal to a voltage controlled oscillator (VCO) control voltage. The PLL is configured to generate the PLL output signal based on the VCO control voltage.