Subsampling Wideband RSSI Circuit for Low Power RF Detection
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Solution Overview
Problem
Typical RSSI circuits in CMOS technologies face limitations in bandwidth, minimum detectable signal, and power consumption when detecting RF signals, particularly in communication and measurement systems.
Innovation Solution
A subsampling RSSI circuit that processes input signals using a sampling frequency to concentrate power in a narrow bandwidth, employing an analog-to-digital converter and a baseband detector to digitize and detect power, while ignoring higher order aliases, thereby reducing power consumption and improving sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a typical RMS power detector or peak detector is used to measure RF signal power, then the circuit can provide power detection capability, but the bandwidth is limited and power consumption is high
Solution Approach 1:
The patent replaces the traditional analog RMS detector or peak detector with a digital signal processing approach. The subsampling ADC converts the RF signal to digital form, and then digital signal processing algorithms compute the power, thereby replacing analog detection mechanisms with digital processing to reduce power consumption while maintaining detection accuracy
Solution Approach 2:
The patent changes the sampling frequency parameter to be lower than the RF signal frequency, creating a subsampling scenario. This parameter change enables the system to process wideband signals with a lower-frequency clock, reducing the power consumption of the ADC and associated circuitry while still capturing the necessary signal information for power measurement
2Ease of manufacture
If a typical power detector is used in CMOS technologies, then the circuit can be integrated, but the minimum detectable signal is relatively high and performance is limited
Solution Approach 1:
The patent segments the power detection function into distinct stages: subsampling ADC conversion, digital signal conditioning, and power computation. This segmentation allows each stage to be optimized independently, with the digital stages implemented in standard CMOS technology, achieving good integration while maintaining high sensitivity through optimized digital processing
Solution Approach 2:
The patent introduces digital signal processing as an intermediary between the ADC and the final power measurement. This intermediary stage allows for flexible signal conditioning, filtering, and computation that enhances the minimum detectable signal performance while remaining compatible with CMOS integration
3Speed
If a wideband RSSI circuit is designed with high bandwidth, then the circuit can detect a wide range of frequencies, but power consumption increases and minimum detectable signal worsens
Solution Approach 1:
The patent employs dynamic subsampling where the sampling frequency can be adjusted based on the input signal characteristics. This dynamic approach allows the system to maintain wideband capability when needed while operating at lower effective sampling rates for power-efficient detection, adapting the bandwidth utilization to match the actual signal requirements
Solution Approach 2:
The patent uses periodic subsampling at a frequency lower than the RF signal frequency. This periodic action with controlled aliasing allows the system to process wideband signals through a lower-frequency ADC, significantly reducing power consumption while maintaining the ability to detect signals across a wide frequency range through proper clocking and digital processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The subsampling RSSI circuit enhances sensitivity and reduces power consumption by shifting wideband RF signals to baseband frequencies, relaxing bandwidth requirements and allowing for digital power detection, thus improving overall performance in RF power detection.
Implementation Method 1
a subsampling circuit that processes an input signal comprising a sampling frequency, fs, wherein the subsampling circuit subsamples the input signal, wherein the input signal is subsampled to concentrate a power in a narrow bandwidth
Implementation Method 2
an analog-to-digital converter (ADC) operatively connected to the subsampling circuit, wherein the ADC digitizes the subsampled signal
Implementation Method 3
a baseband detector operatively connected to the ADC, wherein the baseband detector detects a power from the digitized subsampled signal and creates an output signal. The baseband detector preferably comprises any of a RMS (I2+Q2) detector, and a peak detector
Data Source
AI summary
A Received Signal Strength Indicator (RSSI) circuit includes a subsampling circuit that processes an input signal comprising a sampling frequency, fs, wherein the subsampling circuit subsamples the input signal, wherein the input signal is subsampled to concentrate a power in a narrow bandwidth; an analog-to-digital converter (ADC) operatively connected to the subsampling circuit, wherein the ADC digitizes the subsampled signal; and a baseband detector operatively connected to the ADC, wherein the baseband detector detects a power from the digitized subsampled signal and creates an output signal. The subsampling circuit and the ADC may operate as a single subsampling ADC. The RSSI circuit may further comprise ignoring higher order aliases at a multiple of the sampling frequency if the baseband detector is clocked at the sampling frequency.