Semiconductor Package Substrate Barrier Layer for Precise Line Definition

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Solution Overview

Problem

In the production of high aspect ratio semiconductor package substrates, fully filling through holes with Cu-plating often results in over-plating and poor line definition due to over-plated Cu on resist patterns or during subsequent etching processes.

Innovation Solution

A semiconductor package substrate is created with a core having through holes, where conductive pillars are formed by applying a conductive material over a barrier layer, and the surface plating is removed until the barrier layer is exposed, allowing for the formation of circuit segments with coplanar metal layers that prevent over-etching and ensure precise definition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If through holes are fully filled with Cu-plating, then the through holes are completely filled, but over-plating occurs resulting in poor line definition

Engineering Contradiction:
Improveline definitionVSAvoidCu-plating amount
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

A barrier layer is formed on the inner wall of the through hole before Cu-plating. This preliminary action creates a controlled interface that prevents excessive Cu deposition, thereby maintaining line definition while ensuring complete hole filling.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The barrier layer acts as an intermediary between the through hole wall and the Cu-plating. It controls the plating process by providing a defined surface that prevents uncontrolled Cu growth, thus avoiding over-plating while ensuring complete filling.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If high aspect ratio through holes are filled by plating, then the through holes are filled, but over-plated Cu damages underlying layers

Engineering Contradiction:
Improvelayer protectionVSAvoidplating process control
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The barrier layer serves as a protective intermediary that prevents over-plated Cu from damaging the underlying resin core and circuit patterns. It absorbs the excess plating material, protecting the delicate underlying structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The barrier layer provides beforehand cushioning by being positioned before the Cu-plating process. It acts as a sacrificial layer that prevents damage to underlying structures from over-plating, cushioning the impact of excessive material deposition.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Manufacturing precision

If conductive pillars are formed by plating, then electrical connection is achieved, but over-plating causes poor circuit formation

Engineering Contradiction:
Improvecircuit formation accuracyVSAvoidconductive material amount
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The barrier layer acts as an intermediary that controls conductive material deposition. It provides a defined interface that prevents uncontrolled growth of the conductive pillars, ensuring precise circuit formation while maintaining electrical connectivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The barrier layer changes the deposition parameters of the conductive material by providing a controlled surface with specific surface energy and roughness characteristics. This modifies the plating process to achieve uniform, controlled growth without over-plating.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively prevents over-plating and maintains precise line definition, ensuring accurate circuit formation and preventing damage to underlying layers during the manufacturing process.

Implementation Method 1

forming a plurality of conductive vias by applying a conductive material over a barrier layer, and removing a surface plating portion until the barrier layer is exposed

Methodology Applied
Scientific EffectPlating: Electroplating

Data Source

PatentUS8686568B2Semiconductor package substrates having layered circuit segments, and related methods
Publication Date: 2014.04.01 ADVANCED SEMICON ENG INC
  • US8686568B2 patent drawing
  • US8686568B2 patent drawing
  • US8686568B2 patent drawing

AI summary

The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.