Substrate Barrier Layout for Minimal Underfill Keep-Out Zones
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Solution Overview
Problem
In IC packaging, confining underfill material to the space under the top IC die is challenging, as it tends to flow away or escape to undesired areas, necessitating a larger keep-out zone (KOZ) that increases substrate size and restricts interconnect placement.
Innovation Solution
A barrier feature on the substrate surface, often utilizing existing copper layers, is modified to arrest the flow of underfill material, creating a minimal KOZ without adding process steps, allowing for singulated die sorting and reducing substrate size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a larger keep-out zone is used to confine underfill material, then underfill confinement is improved, but substrate size increases and interconnect placement is restricted
Solution Approach 1:
The substrate surface is segmented into functional zones using barrier features that divide the space between interconnect features. These barriers create discrete regions that confine underfill material to specific areas, preventing it from flowing into keep-out zones while maximizing the usable substrate area for interconnect placement.
2Reliability
If a larger keep-out zone is used to confine underfill material, then underfill confinement is improved, but interconnect placement options are reduced
Solution Approach 1:
The barrier features create local zones with different properties: areas with barriers allow interconnects to be placed closer together since underfill is confined, while areas without barriers maintain traditional spacing. This local differentiation enables optimized interconnect placement that adapts to specific design requirements while maintaining underfill confinement where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The barrier feature effectively confines underfill material, reducing the required KOZ size and enabling singulated die sorting, thus optimizing substrate space and manufacturing efficiency.
Implementation Method 1
a barrier feature on a surface of a substrate or other bottom component in a composite IC device to arrest the flow of underfill material
Data Source
AI summary
An integrated circuit (IC) device package substrate comprises a plurality of first interconnect features to couple to a first IC die, a plurality of second interconnect features to couple to a second IC die, and one or more barrier features on a surface of the substrate. The first interconnect features span a first length in a first direction on the surface of the substrate. The second interconnect features span a second length in the first direction on the surface of the substrate. The second interconnect features are between the first length of the first interconnect features and a first edge of the substrate. The one or more barrier features are between the first and second interconnect features, wherein the one or more barrier features span a third length in the first direction, the third length greater than at least one of the first or second lengths.