Substrate Bias Feedback Reduces Leakage Current
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Solution Overview
Problem
Conventional methods for reducing chip leakage power in SRAM circuits are either costly, slow, or ineffective across various process, voltage, and temperature (PVT) conditions, and often compromise speed or require expensive multi-Vt technologies and die-by-die tweaks.
Innovation Solution
A closed-loop substrate bias feedback system using a low ripple negative charge pump controlled by an operational amplifier to automatically set the reverse bias voltage for transistors, reducing sub-threshold leakage across PVT conditions without affecting standby to active access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional high Vt technology is used to lower current leakage, then leakage current is reduced, but the entire chip speed slows down because high threshold voltage causes all transistors to switch slowly
Solution Approach 1:
The patent applies reverse substrate bias specifically to transistors exhibiting high leakage current, rather than uniformly to all transistors. The system dynamically identifies individual transistors with excessive leakage and applies bias only to those devices, maintaining high-speed operation in low-leakage transistors while suppressing leakage in problematic ones.
Solution Approach 2:
The patent implements a dynamic feedback system that continuously monitors transistor leakage current and adjusts substrate bias in real-time. The system responds to changing PVT conditions and individual transistor characteristics, dynamically applying or removing bias as needed rather than using a static high Vt approach.
2Loss of energy
If multi-Vt technologies are employed to reduce leakage, then leakage current is lowered, but manufacturing cost increases due to additional mask steps required during wafer manufacturing
Solution Approach 1:
The patent changes the operational parameter (substrate bias voltage) of existing transistors rather than requiring physical modifications during manufacturing. By applying reverse substrate bias dynamically, the system achieves leakage reduction equivalent to high Vt transistors without needing additional mask steps or multi-Vt process complexity.
Solution Approach 2:
The patent implements a feedback mechanism that measures actual leakage current and adjusts substrate bias accordingly. This closed-loop system automatically compensates for process variations and identifies which transistors need bias application, eliminating the need for expensive pre-characterization or die-by-die tweaking during manufacturing.
3Loss of energy
If constant substrate reverse bias reference voltage is set at wafer sort by die-by-die tweak, then optimal substrate bias voltage is achieved for each die, but additional test time per die is required and the bias does not change automatically with voltage and temperature
Solution Approach 1:
The patent implements a self-adjusting system that automatically monitors its own leakage current and dynamically modifies substrate bias without external intervention. The feedback system continuously adapts to PVT changes and individual transistor characteristics, eliminating the need for manual die-by-die configuration or periodic recalibration.
Solution Approach 2:
The patent transforms the static die-by-die bias setting into a dynamic, real-time adjustment system. The substrate bias voltage automatically changes in response to temperature variations, supply voltage changes, and measured leakage current, without requiring re-testing or manual intervention.
4Loss of energy
If chip power supply is reduced during standby conditions and brought back to nominal voltages during active mode, then leakage power is reduced during standby, but there is a startup time from standby to active mode
Solution Approach 1:
The patent segments the power management approach by applying substrate bias selectively to individual transistors rather than reducing the entire chip power supply. This allows leakage reduction in standby mode without affecting the overall power supply voltage, enabling immediate wake-up when needed.
Solution Approach 2:
The patent implements periodic or on-demand substrate bias application based on measured leakage current rather than continuous power supply reduction. The system can quickly enable or disable bias as needed, providing immediate response to wake-up events without the delay associated with power supply ramping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves an 85% reduction in worst-case leakage current while maintaining high speed and reducing test time and costs, without the need for expensive multi-Vt technologies or die-by-die tweaks, ensuring optimal performance across all PVT corners.
Implementation Method 1
A first embodiment comprises a closed loop low ripple negative charge pump system
Implementation Method 2
The reverse bias is applied on the bulk/substrate of transistors to increase the threshold voltage of the transistors resulting in leakage reduction
Data Source
AI summary
A method of biasing a circuit includes generating a control bias signal based on a difference between a leakage current of a baseline circuit and a reference signal; applying the control bias signal to a charge pump circuit to set a value of a reverse body bias voltage output from the charge pump, the control bias signal providing analog control of a digital clock of the charge pump circuit; and applying the reverse body bias voltage to a body of the baseline circuit.