Substrate Bias Circuit for Low-Voltage Startup and Leakage Control
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Solution Overview
Problem
IoT devices require extremely low power consumption, necessitating a substrate bias generating circuit that can activate normally at lower supply voltages and minimize leakage current when voltages return to standard levels.
Innovation Solution
A substrate bias generating circuit comprising a first NMOS transistor, a second PMOS transistor, and a third PMOS transistor, along with a resistance element, which provides a substrate bias to reduce the threshold voltage of transistors for activation at low voltages and minimizes leakage current when voltages exceed the threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the supply power voltage is lower than the standard threshold voltage of the transistor, then the transistor cannot be activated normally, but reducing the threshold voltage requires additional circuit complexity
Solution Approach 1:
The patent introduces a substrate bias generating circuit as an intermediary component that produces a bias voltage signal. This bias signal is applied to the substrate of the transistor to dynamically adjust its threshold voltage, enabling normal activation even when the supply voltage is below the standard threshold level.
Solution Approach 2:
The patent changes the threshold voltage parameter of the transistor by applying a substrate bias voltage. The bias generating circuit dynamically adjusts the substrate potential, which directly modifies the transistor's threshold voltage characteristic, allowing the transistor to operate correctly under varying supply voltage conditions.
2Reliability
If the supply power voltage returns to over the standard threshold voltage, then the transistor should return to normal operating state, but without proper bias control leakage current increases
Solution Approach 1:
The substrate bias generating circuit incorporates feedback mechanisms that monitor the supply voltage level and automatically adjust the bias signal accordingly. When the supply voltage returns to normal levels, the feedback control ensures the bias signal is adjusted to minimize leakage current while maintaining proper transistor operation.
Solution Approach 2:
The patent implements dynamic bias control where the substrate bias voltage is not fixed but varies with the supply voltage conditions. The bias generating circuit dynamically adapts the threshold voltage adjustment based on real-time voltage levels, enabling the transistor to transition smoothly between different operating states without excessive leakage.
3Adaptability or versatility
If the threshold voltage of the transistor is reduced to facilitate activation at low voltages, then the transistor can operate at lower supply voltages, but leakage current increases when voltages return to standard levels
Solution Approach 1:
The substrate bias generating circuit provides dynamic threshold voltage adjustment rather than a fixed reduction. The bias voltage changes with supply voltage conditions, enabling low-voltage operation when needed while automatically reducing leakage current when the supply voltage returns to standard levels.
Solution Approach 2:
The patent dynamically changes the threshold voltage parameter based on supply voltage conditions. The substrate bias generating circuit modulates the substrate potential to adjust the threshold voltage, allowing the transistor to adapt its electrical characteristics to match the current operating voltage level.
Data Source
AI summary
A substrate bias generating circuit is provided for generating a substrate bias to a body of a transistor of a functional circuit. The substrate bias generating circuit includes a first transistor and a second transistor which are connected in series between a supply voltage terminal and a ground terminal, and control terminals of the first transistor and the second transistor are coupled to each other. A third transistor includes a terminal electrically coupled to body of one of the first transistor and the second transistor, and another terminal coupled to the body. A resistance element is connected between the terminal of the third transistor and a current input terminal of the first transistor or a current output terminal of the second transistor.