Packaging Substrate Block-Type Via Thermal Dissipation

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Solution Overview

Problem

Advanced semiconductor packages face thermal challenges due to increased power consumption, which degrade IC performance and structural integrity, and existing solutions like metal lids are expensive.

Innovation Solution

A packaging substrate with a core layer and embedded block-type vias that efficiently dissipate heat through conductive pads and vias, eliminating the need for expensive heat sinks or metal lids.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a metal lid is used for heat dissipation, then thermal performance is improved, but manufacturing cost increases

Engineering Contradiction:
Improveheat dissipation performanceVSAvoidmanufacturing cost
Core Design Contradiction:
TemperatureVSEase of manufacture

Solution Approach 1:

The patent extracts the heat dissipation function from the traditional metal lid and relocates it to the substrate's ground pads and power pads. By removing the separate metal lid component and integrating thermal management into the substrate structure itself, the solution eliminates the need for expensive metal lids while maintaining effective heat dissipation through the substrate's conductive pathways.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The ground pads and power pads are given dual functionality: their traditional electrical connection role plus an additional heat dissipation function. By making these existing structural elements serve multiple purposes (electrical grounding/power delivery and thermal management), the patent eliminates the need for dedicated heat dissipation components like metal lids, thereby reducing manufacturing cost while maintaining thermal performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Power

If power consumption is increased, then functionality and performance are improved, but thermal stress and heat generation worsen

Engineering Contradiction:
Improvepower consumptionVSAvoidheat generation
Core Design Contradiction:
PowerVSTemperature

Solution Approach 1:

The patent converts the harmful effect of heat generation into a beneficial thermal management solution by utilizing the substrate's ground pads and power pads as heat dissipation pathways. The heat generated by high power consumption is redirected through the substrate's conductive structures, transforming the problematic thermal byproduct into an integrated thermal management feature that supports higher power operation without excessive temperature rise.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances thermal and power integrity performance by efficiently dissipating heat through the substrate, improving IC performance without the need for costly heat dissipation solutions.

Implementation Method 1

The heat from the chip is transferred to the metal lid via a thermally conductive chip/lid interface. The heat is then transferred from the lid to the ambient atmosphere via convection.

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS10340199B2Packaging substrate with block-type via and semiconductor packages having the same
Publication Date: 2019.07.02 MEDIATEK INC
  • US10340199B2 patent drawing
  • US10340199B2 patent drawing
  • US10340199B2 patent drawing

AI summary

A packaging substrate includes a core layer having a first surface and a second surface. A group of ground pads is disposed on the second surface within a central region. A group of first power pads is disposed on the second surface within the central region. A plurality of signal pads is disposed on the second surface within a peripheral region that encircles the central region on the second surface. A first block-type via is embedded in the core layer within the central region. The group of ground pads is electrically connected to the first block-type via. A second block-type via is embedded in the core layer within the central region. The group of first power pads is electrically connected to the second block-type via.