Semiconductor Substrate Bonding for Ultrafine Pitch Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in extending beyond 40 μm pitches for flip chip solder connections to achieve maximal performance in advanced logic and memory devices through product miniaturization, as existing technologies struggle to maintain efficiency and reliability at finer interconnect pitches.
Innovation Solution
A semiconductor device and manufacturing method involving direct contact between two semiconductor substrates with through vias and conductive contacts, using van der Waals bonds and IR laser-assisted bonding to form dielectric-to-dielectric covalent bonds and reflow solder, eliminating the need for adhesive layers and enabling ultrafine pitch connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional flip chip solder connections are used, then reliability is maintained at coarser pitches, but manufacturing precision deteriorates at ultrafine pitches below 40 μm
Solution Approach 1:
The patent introduces a bonding layer as an intermediary between the first and second semiconductor substrates. This bonding layer contains through vias with conductive contacts that enable direct bonding, serving as a mediator that allows ultrafine pitch connections while maintaining reliability by providing a controlled interface for bonding rather than relying on traditional solder connections at the substrate level
Solution Approach 2:
The patent replaces the traditional mechanical solder connection system with a direct bonding system using van der Waals forces and covalent bonds. By substituting the solder intermediary with direct dielectric-to-dielectric bonding assisted by IR laser heating, the system achieves ultrafine pitch connections with improved manufacturing precision and maintained reliability
2Ease of operation
If adhesive layers are used in substrate bonding, then alignment is facilitated, but device complexity increases due to additional interface issues
Solution Approach 1:
The patent extracts and eliminates the adhesive layer from the bonding structure. By removing this intermediary layer, the design simplifies the interface between substrates, reducing device complexity and potential interface issues while maintaining alignment capability through direct bonding of the bonding layers
Solution Approach 2:
The patent merges the alignment and bonding functions into a single direct bonding process. The bonding layers with integrated through vias and conductive contacts are directly bonded together without adhesive layers, combining the structural support and electrical connection functions in a simplified interface that reduces overall device complexity
3Productivity
If conventional bonding methods are used, then process simplicity is maintained, but productivity decreases at ultrafine pitches due to alignment difficulties
Solution Approach 1:
The patent applies preliminary action by pre-forming the bonding layers with through vias and conductive contacts on each substrate before bonding. This preliminary preparation of the bonding interfaces with integrated alignment features enables faster and more efficient bonding at ultrafine pitches, improving productivity by eliminating the need for complex real-time alignment adjustments during the bonding process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient alignment and bonding of semiconductor substrates at ultrafine pitches, enhancing performance and reliability by eliminating interface issues and achieving high shear strength bonds, thus supporting the miniaturization of advanced devices.
Implementation Method 1
using van der Waals bonds and IR laser-assisted bonding to form dielectric-to-dielectric covalent bonds
Implementation Method 2
using van der Waals bonds and IR laser-assisted bonding to form dielectric-to-dielectric covalent bonds and reflow solder
Data Source
AI summary
A semiconductor device includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate includes a first base, a first bonding layer and a first conductive contact. The first bonding layer has a first through via. The first conductive contact is formed within the first through via. The second semiconductor substrate includes a second base, a second bonding layer and a second conductive contact. The second bonding layer has a second through via. The second conductive contact is formed within the second through via. The first conductive contact is electrically connected to the second conductive contact, and the first bonding layer and the second bonding layer are in direct contact with each other.