Redistribution Substrate Bump Structure for Package Connection Reliability
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Solution Overview
Problem
The reliability and yield of semiconductor packages are hindered by the connection quality between the redistribution layer and the connection bump, which affects board level reliability.
Innovation Solution
A semiconductor package design featuring a redistribution substrate with semiconductor and passive components, encapsulants, and bumps where the bumps have distinct inner and outer portions with the inner portion being taller, allowing for improved electrical contact and reliability through the use of stacked solder balls in openings within the encapsulant, enhancing yield and turnaround time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional metal post formation methods are used, then connection reliability can be achieved, but manufacturing complexity and turnaround time increase
Solution Approach 1:
The patent changes the formation method parameter from traditional metal post formation to direct bump formation through openings in the encapsulant. This parameter change simplifies the manufacturing process while maintaining connection reliability by establishing direct electrical contact between bumps and redistribution layers without requiring complex metal post formation steps.
Solution Approach 2:
The patent extracts and eliminates the intermediate metal post formation step from the traditional manufacturing process. By forming bumps that directly contact the redistribution layers through openings in the encapsulant, the complex metal post formation process is removed, reducing manufacturing complexity while preserving connection reliability.
2Reliability
If traditional metal post formation methods are used, then connection reliability can be achieved, but turnaround time increases
Solution Approach 1:
The patent changes the process parameter from multi-step metal post formation to direct bump formation through encapsulant openings. This parameter change reduces turnaround time by eliminating intermediate formation steps while maintaining connection reliability through direct electrical contact between bumps and redistribution layers.
Solution Approach 2:
The patent performs preliminary action by forming openings in the encapsulant before placing the bumps. This preliminary preparation enables direct bump formation and contact with redistribution layers, eliminating the need for subsequent metal post formation steps and reducing overall turnaround time while ensuring connection reliability.
3Reliability
If connection quality between redistribution layer and connection bump is improved, then board level reliability improves, but manufacturing complexity increases
Solution Approach 1:
The patent extracts and eliminates the complex metal post formation process from the manufacturing flow. By forming bumps that directly contact redistribution layers through encapsulant openings, the patent achieves improved connection quality and board level reliability without increasing manufacturing complexity, as the direct formation method is simpler than traditional multi-step metal post formation.
Solution Approach 2:
The patent changes the manufacturing parameter from complex metal post formation to direct bump formation through openings. This parameter change improves board level reliability by ensuring direct and robust electrical contact between bumps and redistribution layers, while simultaneously reducing manufacturing complexity by eliminating intermediate formation steps.
Data Source
AI summary
A semiconductor package is provided including: a redistribution substrate having an upper surface and a lower surface, opposite to each other, and including redistribution layers; a semiconductor chip disposed on the upper surface of the redistribution substrate and electrically connected to the redistribution layers; an upper encapsulant encapsulating at least a portion of the semiconductor chip and disposed on the upper surface of the redistribution substrate; a passive component disposed on the lower surface of the redistribution substrate and electrically connected to the redistribution layer; a lower encapsulant encapsulating at least a portion of the passive component and disposed on the lower surface of the redistribution substrate, and having a plurality of openings exposing lowermost redistribution layers among the redistribution layers; and a plurality of bumps respectively disposed within the plurality of openings, the bumps respectively including a first portion in contact with the lowermost redistribution layers and a second portion extending from the first portion and protruding partially downwardly of the plurality of openings.