Substrate integrated thin film capacitors using amorphous high-k dielectrics
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Solution Overview
Problem
Current solutions for reducing first droop and power delivery noise in electronic circuits, such as using MIM capacitors, LSCs, and ultra-high-k materials, face issues like increased inductance, manufacturing complexity, and disruption to high-volume processes, making them impractical for advanced power scaling.
Innovation Solution
Integration of thin film capacitors using amorphous high-k dielectric films in the packaging substrate, which can be formed with compatible high-volume manufacturing processes, eliminating the need for high-temperature annealing and allowing for minimal thickness, thus reducing first droop effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MIM capacitors are integrated into the back end of the die, then first droop is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The capacitor functionality is segmented from the die itself and placed in the build-up layers of the package substrate. This allows the die to remain simple while the capacitance function is provided by separate structures in the substrate, reducing back-end die complexity.
Solution Approach 2:
The solution moves from integrating capacitors in the die (2D plane) to placing them in the build-up layers of the package substrate (3D space above the die). This dimensional transition allows capacitance to be added without increasing die complexity.
2Reliability
If land-side capacitors are used, then first droop is addressed, but parasitic inductance increases due to long electrical path
Solution Approach 1:
Capacitors are placed locally in the build-up layers immediately adjacent to the die, creating a localized capacitance solution. This proximity minimizes the electrical path length and reduces parasitic inductance compared to distant land-side capacitors.
3Reliability
If ultra-high-k materials like PZT and BaTiO3 are used, then capacitance is improved, but manufacturing complexity increases due to high-temperature annealing requirements
Solution Approach 1:
The patent changes the material parameter from ultra-high-k crystalline materials (requiring high-temperature annealing) to amorphous high-k dielectric materials. This parameter change allows achieving high capacitance without the need for disruptive high-temperature processing steps.
Solution Approach 2:
The solution replaces the thermal processing mechanism (high-temperature annealing required for crystal structure formation) with a deposition-based approach that forms amorphous high-k dielectric films. This substitution eliminates the need for high-temperature equipment and processes.
4Reliability
If prefabricated high-k dielectric films are used, then capacitance is improved, but package thickness increases
Solution Approach 1:
Instead of using complete prefabricated capacitor films with full thickness, the patent uses thin amorphous high-k dielectric layers deposited directly in the build-up layers. This partial approach provides sufficient capacitance while maintaining thin profile and avoiding excessive Z-height increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The amorphous high-k dielectric films provide efficient capacitance close to the die, minimizing first droop and power delivery noise without increasing the package's form factor or manufacturing complexity, while being compatible with existing processes.
Implementation Method 1
the capacitor comprises: a first electrode disposed over the dielectric layer; a capacitor dielectric layer over the first electrode, wherein the capacitor dielectric layer is an amorphous dielectric layer; and a second electrode over the capacitor dielectric layer
Data Source
AI summary
Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.