Substrate Cavities for Photonic Integrated Circuit Underfill Management
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Solution Overview
Problem
Conventional flip-chip bonding using underfill materials can lead to inefficient operation of thermo-optic phase shifters (TOPS) in photonic integrated circuits (PICs) due to the underfill filling the TOPS cavity, which increases thermal conductivity and reduces power efficiency by a factor of 3-6.
Innovation Solution
Creating cavities in the substrate below the TOPS heaters to prevent the underfill from filling the TOPS cavity, allowing an air gap that maintains efficient operation by using surface tension to cause the underfill to flow around the cavities and adhere the PIC to the substrate without filling them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If underfill is used to bond the photonic integrated circuit to the substrate, then adhesion strength is improved, but thermal conductivity increases causing power efficiency to deteriorate
Solution Approach 1:
The substrate is segmented by creating cavities beneath the TOPS heaters, dividing the substrate into regions separated by air gaps. This segmentation prevents the underfill from forming a continuous thermal path to the TOPS heaters, thereby maintaining adhesion strength while reducing thermal conductivity and improving power efficiency.
Solution Approach 2:
The underfill material is extracted or removed from the cavity regions beneath the TOPS heaters by designing the bonding process to allow underfill to flow around the cavities. This extraction eliminates the harmful thermal conduction path while preserving the beneficial adhesion properties of the underfill in the bonding regions.
2Strength
If underfill flows into the TOPS cavity, then adhesion is improved, but thermal insulation deteriorates
Solution Approach 1:
Air gaps introduced through substrate cavities act as intermediary thermal barriers between the underfill and the TOPS heaters. These air gaps mediate the thermal interaction by providing high thermal resistance, preventing heat from conducting through the underfill to the substrate, thereby maintaining thermal insulation while allowing adhesion in other regions.
3Ease of manufacture
If the substrate is made flat and continuous, then manufacturing is simplified, but stress concentration occurs on connecting bumps
Solution Approach 1:
The substrate is segmented by introducing cavities that create compliance zones. These segmented regions allow the substrate to flex and accommodate thermal expansion differences between the PIC and substrate, thereby reducing stress concentration on the connecting bumps and pillars while maintaining ease of manufacture through standard cavity fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces stress on connecting bumps or pillars and maintains efficient operation of TOPS by preventing the underfill from filling the cavities, thereby lowering power consumption and enhancing overall system efficiency.
Implementation Method 1
each cavity of the set of cavities when coupled to the PIC creates a surface tension when exposed to an underfill to cause the underfill to flow around each cavity
Data Source
AI summary
A method for making an apparatus, a system, and apparatus, the apparatus and system each comprising a substrate with a top side, wherein the substrate has a set of cavities in the top side of the substrate, wherein the substrate has a set of conductive elements on the top side of the substrate arranged to electrically couple with a set of conductive elements of a photonic integrated circuit (PIC), wherein each cavity of the set of cavities when coupled to the PIC creates a surface tension when exposed to an underfill to cause the underfill to flow around each cavity.