Substrate Cavity Chip Stacking for Thin Reliable Semiconductor Packages
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Solution Overview
Problem
There is a need for semiconductor packages with increased space utilization and high reliability, as reducing the thickness of chip layers can lead to cracks or malfunctions during manufacture, and existing technologies struggle to balance compactness and structural integrity.
Innovation Solution
A semiconductor package design featuring a substrate cavity within a package base substrate with stacked insulating layers, conductive vias, and solder resist layers, where semiconductor chips are partially housed within the cavity and partially protrude above it, connected by bonding wires, and covered by a mold layer for enhanced support and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of chip layers is reduced to increase compactness, then package thickness decreases and space utilization improves, but cracks or malfunctions occur during manufacture reducing reliability
Solution Approach 1:
The substrate is divided into a cavity portion and a non-cavity portion, creating distinct functional zones. The cavity portion accommodates stacked semiconductor chips while the non-cavity portion provides structural support and houses bonding wires, separating the compacting function from the structural support function to prevent cracks during manufacturing
Solution Approach 2:
The substrate cavity extends in the vertical direction (thickness direction) rather than only in horizontal planes. This vertical extension allows the cavity to accommodate thick stacked chips while maintaining a compact overall package thickness, resolving the contradiction between chip thickness and package compactness
2Quantity of substance
If multiple chips are disposed within one semiconductor package to increase integration, then space utilization improves, but device complexity increases
Solution Approach 1:
Multiple semiconductor chips are stacked vertically within the substrate cavity like nested dolls, with each chip positioned on top of the previous one. This vertical nesting arrangement increases the number of chips per package while maintaining a compact structure and simplifying inter-chip connections through direct stacking rather than lateral routing
Solution Approach 2:
The patent transitions from horizontal chip arrangement to vertical stacking in the thickness direction. This dimensional change allows multiple chips to be integrated within one package without significantly increasing the package's planar area, and the substrate cavity structure simplifies the complexity by providing a dedicated vertical accommodation space
Data Source
AI summary
A semiconductor package includes a package base substrate including a substrate cavity formed therein, the substrate cavity extending from a top surface of the package base substrate downwardly toward a bottom surface of the package base substrate. The package base substrate further includes a plurality of base insulating layers, a plurality of substrate wiring patterns extending along at least one of a top surface and a bottom surface of each of the plurality of base insulating layers, and a plurality of substrate conductive vias which pass through at least one of the plurality of base insulating layers and are connected to the plurality of substrate wiring patterns. The semiconductor package further includes a plurality of semiconductor chips disposed at a bottom of the substrate cavity and stacked in a direction perpendicular to a plane of the package base substrate.