Substrate Cavity Embedding for Signal Integrity
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Solution Overview
Problem
Existing techniques to reduce interconnection distance between semiconductor devices, such as routing signal traces through a flexible circuit layer, are not cost-effective and do not significantly reduce stray capacitances, leading to increased propagation delay and degraded signal quality.
Innovation Solution
A method involving the formation of a cavity in a substrate to house a first device, with a second device attached via bumps, utilizing either drilling or a semi-additive process to achieve the shortest interconnection length between devices, thereby directly attaching them through a flip-chip process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If signal traces are routed through a flexible circuit layer, then interconnection distance is reduced, but manufacturing cost increases and stray capacitances are not significantly reduced
Solution Approach 1:
The first device is embedded within a cavity formed in the substrate, nesting the device inside the substrate structure. This eliminates the need for separate flexible circuit layers while achieving short interconnection distances through direct bump connections between devices.
Solution Approach 2:
The invention transitions from planar routing on flexible circuit layers to three-dimensional embedding within substrate cavities. Devices are positioned at different depths and connected via vertical bump interconnections, utilizing the third dimension to minimize signal path length.
2Length of stationary object
If signal traces are routed through a flexible circuit layer, then interconnection distance is reduced, but propagation delay increases due to stray capacitances
Solution Approach 1:
Embedding the first device within the substrate cavity removes it from the planar signal routing path, enabling direct vertical connections via bumps. This nesting approach minimizes the signal path length and reduces stray capacitance exposure, thereby decreasing propagation delay.
Solution Approach 2:
By moving from two-dimensional planar routing to three-dimensional vertical connections through bump interconnections, the signal path is shortened and stray capacitance is minimized, directly reducing propagation delay.
3Length of stationary object
If devices are directly attached via bumps, then interconnection length is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The cavity is formed in the substrate before the first device is embedded, and bumps are prepared on both devices prior to attachment. This preliminary preparation of the embedding structure and bump configurations enables precise alignment during the flip-chip process, reducing the actual manufacturing precision demands during final assembly.
Data Source
AI summary
An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device.