Circuit Substrate Cavity Layout Without Floor Plate Exposure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packaging methods face challenges in efficiently arranging and connecting multiple semiconductor dies within a compact package, leading to issues with electrical connectivity, thermal management, and package thickness.
Innovation Solution
The method involves forming a redistribution layer on a carrier with multiple dielectric and metallization layers, bonding semiconductor dies to this layer, and then encapsulating them in a molding compound. The package is then connected to a circuit substrate with a cavity that accommodates additional semiconductor dies, enhancing electrical connectivity and reducing package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If multiple semiconductor dies are arranged and packaged in a compact configuration, then package thickness is reduced, but electrical connectivity and thermal management become more difficult to achieve
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacking of semiconductor dies. Multiple dies are arranged in vertical layers on the circuit substrate, with through-substrate vias providing electrical interconnections between layers. This vertical dimensionality change enables compact packaging while maintaining electrical connectivity through the Z-axis rather than requiring extensive lateral routing.
Solution Approach 2:
The patent introduces intermediate structures including redistribution layers (RDLs) and through-substrate vias that act as mediators for electrical connections. These intermediary elements facilitate signal routing between stacked dies and the external substrate, solving the connectivity challenge imposed by the compact three-dimensional arrangement.
2Length of moving object
If multiple semiconductor dies are arranged and packaged in a compact configuration, then package thickness is reduced, but thermal management becomes more difficult to achieve
Solution Approach 1:
The patent introduces thermal interface materials and heat dissipation structures as intermediary elements between stacked dies and the circuit substrate. These thermal mediators facilitate heat transfer from the compact die stack to the substrate's thermal management system, addressing thermal challenges in the three-dimensional configuration.
3Ease of manufacture
If floor plate is exposed during cavity formation, then manufacturing process is simplified, but manufacturing precision and reliability are compromised
Solution Approach 1:
The patent applies different properties to different regions of the cavity formation process. The cavity is formed with controlled depth to expose only specific local areas where needed, while protecting or leaving covered other regions. This localized approach to cavity formation achieves the necessary manufacturing precision without compromising the overall ease of the process.
Data Source
AI summary
A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.