Substrate Cavity Multi-Die Package With RDL Interconnect Stacking
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization, higher speed, and lower power consumption, requiring innovative packaging techniques for semiconductor dies, especially in stacked semiconductor devices like 3DICs, which need to be cost-effective and provide high-performance connections.
Innovation Solution
A package structure with stacked memory and logic dies connected through a redistribution layer (RDL) and interconnect structures, utilizing u-bump flip chip and metal-polymer hybrid bonding, allowing for high-density connections and reliable communication, with optional heat dissipation and mechanical support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional separate packaging techniques are used for semiconductor dies, then manufacturing process is simpler, but device size is larger and integration density is lower
Solution Approach 1:
The patent combines multiple semiconductor dies and their packaging structures into a single integrated package-on-package assembly. Multiple dies are mounted on a common substrate with shared interconnect structures, eliminating the need for separate packaging of each die and reducing overall device volume while maintaining individual die functionality.
Solution Approach 2:
The patent implements a nested packaging structure where one packaged die is placed within or upon another packaged die, creating a hierarchical arrangement. This nested configuration allows multiple dies to occupy a compact three-dimensional space, significantly reducing the footprint compared to traditional side-by-side packaging.
2Volume of moving object
If stacked semiconductor devices are used to reduce form factor, then device size is smaller, but manufacturing complexity and cost increase
Solution Approach 1:
The patent divides the stacked device into modular packaged dies that can be independently fabricated and tested before final assembly. Each die is packaged separately with its own interconnect structures, allowing for standardized manufacturing processes and easier replacement or upgrading of individual modules, thereby reducing overall manufacturing complexity.
Solution Approach 2:
The patent performs preliminary packaging and interconnect formation on each die before stacking. This preliminary action allows each die to be prepared independently with pre-formed bonding pads and interconnect structures, simplifying the final stacking process and enabling parallel manufacturing of multiple dies, which reduces overall manufacturing complexity and cost.
3Reliability
If more interconnect structures are added for high-density connections, then connection reliability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent designs universal interconnect structures that serve multiple functions: electrical connection, mechanical support, and thermal management. The same interconnect elements used for signal transmission also provide structural reinforcement and heat dissipation pathways, reducing the need for additional specialized components and simplifying the overall device architecture.
Solution Approach 2:
The patent employs composite interconnect structures combining different materials with complementary properties. For example, metal interconnects provide electrical conductivity while polymer matrices provide mechanical support and insulation. This composite approach achieves high connection reliability through material properties rather than increased structural complexity.
Data Source
AI summary
A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.