Substrate Chip Transfer Using Reusable Alignment Marks

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Solution Overview

Problem

Existing chip-on-wafer manufacturing processes do not effectively reuse alignment marks, which are crucial for ensuring alignment and measuring misalignment between chips and substrates, leading to inefficiencies and potential errors in the bonding process.

Innovation Solution

A method involving the temporary bonding of chips to a first substrate, which includes alignment marks, followed by separation and reuse of these marks, allowing for accurate alignment and misalignment measurement without the need for reformation, and enabling the reuse of the first substrate with the alignment marks intact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If alignment marks are used for ensuring alignment and measuring misalignment during chip bonding, then alignment precision is improved, but the alignment marks cannot be reused leading to loss of time and resources

Engineering Contradiction:
Improvealignment precisionVSAvoidtime for mark reformation
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The invention applies the discarding and recovering principle by separating the alignment marks from the first substrate after bonding, and recovering them for reuse in subsequent bonding processes. The alignment marks are discarded from their original substrate context but recovered as reusable components, eliminating the need for reformation and reducing time loss while maintaining alignment precision.

Inventive Principle:
Principle #34Discarding and recovering

2Manufacturing precision

If alignment marks are permanently attached to the first substrate, then alignment precision is maintained, but the first substrate cannot be reused leading to loss of substance

Engineering Contradiction:
Improvealignment precisionVSAvoidfirst substrate
Core Design Contradiction:
Manufacturing precisionVSLoss of substance

Solution Approach 1:

The invention applies segmentation by dividing the bonding system into separable components: the first substrate, the alignment marks, and the chips. This segmentation allows the alignment marks to be detached from the first substrate while maintaining their integrity, enabling both the substrate and marks to be reused without compromising alignment precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The alignment marks are discarded from the first substrate after bonding but recovered for reuse. This prevents the loss of the first substrate while maintaining alignment precision through the recovered marks, addressing both the precision and substance loss concerns.

Inventive Principle:
Principle #34Discarding and recovering

3Manufacturing precision

If new alignment marks are formed for each bonding process, then alignment precision can be ensured, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvealignment precisionVSAvoidmark reformation process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The invention applies self-service by making the alignment marks themselves reusable across multiple bonding processes. Instead of requiring a complex reformation process for each bonding operation, the marks serve themselves by being recovered and reused, simplifying the overall device complexity while maintaining alignment precision.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20240079403A1Method for manufacturing substrate with chips, and substrate processing device
Publication Date: 2024.03.07 TOKYO ELECTRON LTD
  • US20240079403A1 patent drawing
  • US20240079403A1 patent drawing
  • US20240079403A1 patent drawing

AI summary

A method of manufacturing a substrate with chips includes the following (A) and (B):(A) preparing a stacked substrate, the stacked substrate including: a plurality of chips; a first substrate to which the plurality of chips are temporarily bonded; and a second substrate bonded to the first substrate via the plurality of chips; and(B) separating the plurality of chips bonded to the first substrate and the second substrate, from the first substrate, in order to bond the plurality of chips to one surface of a third substrate including a device layer.In this method, the first substrate, from which the plurality of chips are separated, includes alignment marks that are used to ensure alignment when the first substrate and the plurality of chips are bonded together, or that are used to measure misalignment after the first substrate and the plurality of chips are bonded together.