Substrate Circuit Layout for Chip Cracking Resistance
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Solution Overview
Problem
Conventional semiconductor structures face chip cracking during molding or hot pressing due to concentrated reaction forces from narrow wires, which are insufficient to disperse the stress exerted on the chip.
Innovation Solution
A substrate structure design with widened conductive traces within the chip placement region, increasing the contact area and dispersing the reaction force, including meandering or multiple traces, and using conductive vias to connect circuits, thereby reducing stress concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If narrow wires are used to increase circuit density, then more circuits can be accommodated on the substrate, but the contact surface with the chip becomes extremely small resulting in concentrated reaction force and chip cracking
Solution Approach 1:
The narrow wire is segmented into multiple parallel conductive traces within the chip placement region. This segmentation distributes the contact area across multiple traces, reducing the concentrated reaction force on any single point of the chip while maintaining the overall circuit density through the parallel arrangement of traces.
Solution Approach 2:
The conductive trace structure transitions from a single narrow line to a multi-trace configuration that expands in the lateral dimension within the chip placement region. This dimensional change increases the contact surface area with the chip without increasing the overall footprint, thereby dispersing reaction forces while maintaining compact circuit density.
2Reliability
If the wire width is increased to disperse reaction force, then chip cracking risk is reduced, but the circuit density and number of circuits per unit area decreases
Solution Approach 1:
Multiple narrow conductive traces are merged into a unified circuit structure within the chip placement region. This merging creates an effective wide trace that disperses reaction forces across the chip surface while the individual traces maintain the routing efficiency and density of narrow wires. The combined structure achieves both reliability and productivity goals.
Solution Approach 2:
The conductive traces within the chip placement region are designed with meandering or curved paths rather than straight lines. This curvature increases the contact area with the chip surface in a compact space, dispersing reaction forces effectively while maintaining high circuit density through efficient space utilization.
3Ease of manufacture
If long straight wires are used to connect circuits, then routing is simplified, but the reaction force concentration on the chip is extremely high at contact positions
Solution Approach 1:
The straight wire routing is replaced with meandering or curved conductive traces within the chip placement region. This curvature transformation maintains routing flexibility and manufacturing simplicity while significantly increasing the contact area with the chip, thereby dispersing the reaction force and reducing stress concentration at any single contact point.
Data Source
AI summary
A substrate structure includes an insulating layer and a circuit structure disposed on an upper surface of the insulating layer. The upper surface of the insulating layer includes a chip placement region for placing a chip. The circuit structure includes a first circuit located outside the chip placement region and having a first conductive trace, and a second circuit located within the chip placement region and having a second conductive trace. A width of a region covered by the second circuit is greater than a width of the first circuit. Therefore, the width of the region covered by the circuit passing through the chip placement region is widened and is greater than the width of the circuit outside the chip placement region, thereby increasing the contact area between the chip and the circuit, and dispersing the reaction force from the circuit that the chip receives during hot pressing process.