Substrate Circuit Protection Layers for Yield-Safe Device Manufacturing

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Solution Overview

Problem

The manufacturing process of electronic devices faces challenges in improving yield and increasing process convenience, particularly in forming and testing circuits on substrates while ensuring protection and efficient connection between different circuit components.

Innovation Solution

A method involving the formation of protection layers on both surfaces of a substrate, with specific steps for forming and testing circuits, including the use of protection layers and connection patterns to protect and connect the circuits, and the subsequent integration of light-emitting elements and ICs, enhancing the manufacturing process by improving yield and convenience.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If protection layers are formed on both surfaces of the substrate, then circuit protection during manufacturing is improved, but device complexity increases

Engineering Contradiction:
Improvecircuit protectionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the protection mechanism into separate protection layers for the first surface and second surface of the substrate. Each protection layer is independently formed to protect circuits on its respective surface, allowing for targeted protection without requiring a complex unified structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extends protection from a single surface to both surfaces of the substrate by adding protection layers in the vertical dimension. This bidirectional approach provides comprehensive circuit protection while maintaining a relatively simple planar structure on each surface.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If multiple protection layers and connection patterns are formed, then manufacturing precision is improved, but process complexity increases

Engineering Contradiction:
Improvecircuit formation precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent forms protection layers on both surfaces of the substrate before completing all circuit formation steps. This preliminary protection ensures that subsequent processing steps can be performed with higher precision without damaging underlying circuits, while the protection layers are removed after serving their protective function.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protection layers serve as intermediary elements that temporarily protect circuits during manufacturing processes. These layers are formed, used for protection, and then removed, acting as a mediator that enables precise circuit formation without permanently increasing device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If circuits are tested after formation, then product reliability is improved, but manufacturing time increases

Engineering Contradiction:
Improveproduct reliabilityVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements circuit testing after the formation of protection layers and connection patterns, allowing for early detection of manufacturing defects. This preliminary testing approach ensures product reliability by identifying issues before final assembly, while the structured process minimizes additional time through efficient test integration.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20230387375A1Method of manufacturing electronic device
Publication Date: 2023.11.30 INNOLUX CORP
  • US20230387375A1 patent drawing
  • US20230387375A1 patent drawing
  • US20230387375A1 patent drawing

AI summary

A method of manufacturing an electronic device includes the following steps. A substrate is provided, and the substrate has a first surface, a second surface opposite to the first surface and a side surface between the first surface and the second surface. A first circuit is formed on the first surface. The first circuit includes a transistor, a plurality of pads which comprises a first bonding pad, a second bonding pad, a first conductive pad and a first passivation layer. The first passivation layer is disposed on the transistor. The first bonding pad, the second bonding pad and the first conductive pad are respectively disposed on the first passivation layer. A first protection layer is formed on one of the first surface and the second surface. A first cutting lane is formed on the substrate.