Substrate Structure With Conductive Posts Eliminating TSV Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high fabrication cost and complexity of 3D chip stacking electronic packages due to the need for precise silicon substrates and through-silicon vias (TSVs) with a limited depth-to-width ratio, which results in high material consumption and time-consuming wet etching processes, and potential bridging or leakage issues from copper ion diffusion during chemical mechanical polishing (CMP).
Innovation Solution
A substrate structure with conductive posts on a carrier, where the carrier is ground and etched to expose the posts, and a dielectric layer encapsulates them, reducing the length-to-width ratio and eliminating the need for TSVs, thus lowering fabrication costs and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) with limited depth-to-width ratio are used, then electrical connection is achieved, but fabrication cost and complexity increase due to precise substrate requirements and time-consuming wet etching processes
Solution Approach 1:
The patent extracts the conductive function from traditional TSVs by using conductive posts that extend only partially through the substrate thickness. This eliminates the need for complete through-vias and their associated complex fabrication processes including precise substrate thinning and extensive wet etching, while still achieving the required electrical connection function.
Solution Approach 2:
Instead of creating holes through the entire substrate and filling them (traditional TSV approach), the patent inverts the approach by forming conductive posts that rise from the substrate surface and are then encapsulated by dielectric material. This reversal simplifies the fabrication process by eliminating the need for precise substrate thinning and extensive etching.
2Manufacturing precision
If wet etching process is used to remove silicon substrate, then TSVs are exposed, but fabrication time and chemical solution consumption increase
Solution Approach 1:
The patent removes the time-consuming wet etching step by extracting it from the fabrication process. Conductive posts are formed to extend beyond the substrate surface, allowing direct exposure without requiring chemical etching of the substrate. This dramatically reduces fabrication time and chemical solution consumption while maintaining the precision of conductive element exposure.
3Manufacturing precision
If copper ion diffusion occurs during CMP process, then TSVs are formed, but bridging or leakage issues arise
Solution Approach 1:
The patent applies preliminary action by forming the conductive posts before the substrate is thinned or processed further. The posts are created with controlled dimensions and positions, and then the substrate is processed around them. This sequence prevents copper ion diffusion during subsequent CMP processes, as the conductive material is already in its final configuration and protected by the encapsulation approach.
Solution Approach 2:
The patent introduces dielectric material as an intermediary that encapsulates the conductive posts. This dielectric layer acts as a barrier that prevents copper ion diffusion during subsequent processing steps like CMP, thereby eliminating bridging or leakage issues while maintaining the electrical connection function of the conductive posts.
4Length of stationary object
If substrate thickness is reduced to 100 um, then TSV depth is limited, but fabrication cost increases due to extensive material removal
Solution Approach 1:
The patent inverts the traditional approach by not requiring the substrate to be thinned to expose conductive elements. Instead, conductive posts are formed to extend from the substrate surface, and the substrate maintains its original thickness. This eliminates the need for extensive material removal processes while achieving the same functional result, thereby reducing fabrication cost and complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs, increases product yield, and prevents bridging or leakage issues by minimizing the depth-to-width ratio of conductive posts and eliminating the need for TSVs, while meeting miniaturization requirements.
Implementation Method 1
the carrier is ground and etched to expose the posts
Implementation Method 2
a dielectric layer encapsulates them
Data Source
AI summary
A substrate structure is provided, which includes: a substrate body having opposite first and second surfaces; a plurality of conductive posts formed on the first surface of the substrate body and electrically connected to the substrate body; and a dielectric layer formed on the first surface of the substrate body for encapsulating the conductive posts, wherein one end surfaces of the conductive posts are exposed from the dielectric layer. Therefore, the present invention replaces the conventional silicon substrate with the dielectric layer so as to eliminate the need to fabricate the conventional TSVs (Through Silicon Vias) and thereby greatly reduce the fabrication cost. The present invention further provides an electronic package having the substrate structure and a fabrication method thereof.