Redistribution Substrate Connection Structure for Thermal-Stable Packaging
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Solution Overview
Problem
Current semiconductor packages face challenges in efficiently connecting redistribution substrates and mounting semiconductor chips, which affects thermal stability and manufacturing productivity.
Innovation Solution
A semiconductor package design that includes a connection structure with a connection substrate and posts, where the connection substrate has a core layer, conductive patterns, and layers that vertically penetrate, allowing for improved electrical connections and thermal dissipation, and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a connection structure with connection substrate and posts is used to connect redistribution substrates, then thermal stability is improved through better heat dissipation, but device complexity increases due to additional structural components
Solution Approach 1:
The connection substrate integrates multiple functions into a single component: it provides mechanical support for mounting the semiconductor chip, establishes electrical connections through conductive patterns, and enables thermal dissipation through its structural design. This merging of support, connection, and heat dissipation functions into one component improves thermal stability while managing structural complexity.
Solution Approach 2:
The connection substrate serves multiple purposes simultaneously: it acts as a mounting platform for the semiconductor chip, provides electrical interconnection between substrates via conductive patterns and posts, and functions as a heat dissipation pathway. This multi-functionality addresses the technical contradiction by improving thermal stability without proportionally increasing device complexity.
2Stability of the object's composition
If thicker semiconductor chips are mounted to improve thermal dissipation, then thermal stability is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The connection substrate is designed with a distinct structure that includes a core layer, upper layer, and lower layer, providing segmented zones for different functions. The mounting area is specifically configured with enhanced surface area and positioning features that accommodate thicker chips, distributing mechanical and thermal stresses more effectively and reducing precision requirements during mounting.
Solution Approach 2:
The connection substrate features localized design optimizations: the mounting area has increased surface area and specific geometric characteristics that improve chip attachment, while conductive patterns are strategically positioned to optimize thermal pathways. This local quality enhancement at critical areas allows thicker chips to be mounted with reduced precision requirements while maintaining thermal stability.
3Manufacturing precision
If complex photoresist-based copper pillar formation is used to achieve precise electrical connections, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The invention extracts the complex multi-step photoresist-based copper pillar formation process and replaces it with a simplified structure using posts and conductive patterns on the connection substrate. This extraction removes unnecessary manufacturing complexity while maintaining precise electrical connections through the posts that extend from the lower layer through the core layer to the upper layer, thereby improving productivity without sacrificing connection precision.
Solution Approach 2:
The connection substrate is pre-configured with conductive patterns and post structures during substrate fabrication, establishing precise electrical connection pathways before chip mounting. This preliminary action defines the connection geometry in advance, eliminating the need for complex post-processing steps like photoresist-based copper pillar formation, thus improving both precision and productivity.
Data Source
AI summary
A semiconductor package, including a first redistribution substrate, a semiconductor chip on the first redistribution substrate, a connection structure on the first redistribution substrate and spaced apart from the semiconductor chip, the connection structure including a connection substrate and a post on the connection substrate, a second redistribution substrate on the semiconductor chip and the connection structure, and a molding layer between the first redistribution substrate and the second redistribution substrate, the molding layer encapsulating the semiconductor chip and the connection structure, wherein the connection substrate includes a conductive pattern that vertically penetrates the connection substrate, the post is in contact with a top surface of the conductive pattern, and a width of the post is less than a width of the connection substrate.