Substrate Connector With Columnar Conductors For High Routing Density

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Solution Overview

Problem

Current integrated circuit packaging technologies face challenges in efficiently connecting multiple dies or packages with high routing density and precise alignment, leading to limitations in space utilization and electrical connectivity.

Innovation Solution

The use of a substrate connector with a patch substrate layer and an interposer layer, featuring columnar conductors and varying pitches, allows for efficient electrical interconnections between integrated circuit packages and printed circuit boards, enabling reduced routing density and improved alignment tolerances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional interposers with force fit plugs are used to connect integrated circuit packages, then electrical interconnections can be established, but the pitch between adjacent plugs is limited to at least 300 microns which reduces routing density

Engineering Contradiction:
Improverouting densityVSAvoidplug pitch limitation
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The interposer is divided into multiple layers (first interposer layer, second interposer layer, third interposer layer) with different functions. The first layer provides mechanical support with larger pitch holes, the second layer provides electrical interconnections with columnar conductors, and the third layer provides additional routing. This segmentation allows each layer to be optimized independently, enabling higher routing density without being constrained by the 300 micron pitch limitation of traditional single-layer interposers.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If multiple integrated circuit dies are stacked to increase space utilization, then space efficiency improves, but alignment precision and electrical connectivity become more difficult to achieve

Engineering Contradiction:
Improvespace utilizationVSAvoidalignment precision
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

Multiple interposer layers are nested within each other, with the first interposer layer containing support structures, the second layer containing columnar conductors for electrical interconnection, and the third layer providing additional routing paths. This nested multi-layer structure enables complex three-dimensional electrical interconnections between stacked integrated circuit dies while maintaining alignment precision through the hierarchical organization of conductive elements across different layers.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Quantity of substance

If the pitch between connection terminals is reduced to increase routing density, then more connections can be made in limited space, but alignment tolerances become more difficult to maintain

Engineering Contradiction:
Improvenumber of connection terminalsVSAvoidalignment tolerance
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent transitions from a two-dimensional arrangement of connection terminals to a three-dimensional multi-layer structure. Columnar conductors extend vertically through the interposer layers, allowing electrical connections to be made in the vertical dimension rather than only in the horizontal plane. This dimensional change enables higher routing density by stacking connection paths vertically while maintaining acceptable alignment tolerances, as the vertical alignment can be controlled through precise layer thickness control and conductor positioning.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7495330B2Substrate connector for integrated circuit devices
Publication Date: 2009.02.24 INTEL CORP
  • US7495330B2 patent drawing
  • US7495330B2 patent drawing
  • US7495330B2 patent drawing

AI summary

In one embodiment, a stack is assembled comprising a first integrated circuit package, and a substrate connector which connects the integrated circuit package to a circuit board. In one embodiment, the substrate connector includes an interposer substrate and a patch substrate bonded to the interposer substrate. Each substrate includes columnar conductors extending through the substrate to connect to another layer. Other embodiments are described and claimed.