Substrate-Integrated Die-to-Die Links for Dense Multi-Die Packaging
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Solution Overview
Problem
Existing semiconductor devices require separate and external die-to-die links that occupy valuable substrate space and do not account for die-to-die variations, necessitating a more robust and scalable integration solution.
Innovation Solution
Integrate die-to-die links within the packaging substrate, forming them only where needed, using a substrate with alternating conducting and dielectric layers to accommodate die-to-die spacing and routing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If die-to-die links are implemented using external interposers or interconnect bridges, then the links can be established between dies, but valuable substrate space is occupied and the structure becomes more complex
Solution Approach 1:
The patent merges the die-to-die link structure with the packaging substrate by integrating the link layers directly into the substrate during manufacturing. This eliminates the need for separate external interposers or interconnect bridges, thereby reducing substrate space while maintaining link functionality. The link layers are formed as part of the substrate stack, combining what were previously separate components into a unified structure.
Solution Approach 2:
The patent transitions from a planar, external link structure to a three-dimensional integrated structure within the substrate. By stacking multiple link layers at different heights and using vertical vias to connect them, the solution utilizes the vertical dimension to reduce the horizontal footprint on the substrate, thereby saving valuable substrate space while maintaining robust die-to-die connectivity.
2Adaptability or versatility
If separate external die-to-die links are used, then the links can be implemented, but they do not account for die-to-die variations and require later coupling
Solution Approach 1:
The patent performs preliminary action by pre-forming multiple link layers within the substrate during the substrate manufacturing process, before the dies are attached. This allows the link structure to be established in advance with proper accounting for die-to-die variations. The link layers are positioned and configured in the substrate to accommodate potential variations in die placement, eliminating the need for complex post-attachment adjustments.
Solution Approach 2:
The integrated link structure serves multiple functions simultaneously: it provides electrical connectivity between dies, accommodates die-to-die positioning variations, and is built into the substrate during a single manufacturing process. This multi-functional design simplifies the overall manufacturing process by eliminating separate steps for link creation and die attachment, while maintaining adaptability to variations.
3Productivity
If die-to-die links are integrated within the substrate, then substrate space is reduced and dies are directly coupled, but the manufacturing process requires precise layer integration
Solution Approach 1:
The patent segments the link structure into multiple discrete link layers that can be independently formed and positioned within the substrate. Each link layer can be manufactured with standard precision using conventional semiconductor fabrication techniques, and the segmented approach allows for easier integration compared to forming a single complex link structure. This segmentation reduces the overall manufacturing precision requirement while achieving efficient substrate space utilization.
Data Source
AI summary
Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including two or more high-density layers for die-to-die interconnections. In various embodiments, a semiconductor device includes a substrate comprising two or more first layers and a second layer. A first length of the two or more first layers can be less than a second length of the second layer. The semiconductor device can further include a first die coupled to the second layer of the substrate and a second die coupled to the second layer. At least one of the two or more first layers comprises a connector coupling the first die to the second die.