Substrate-on-Die Package Layout for Low-Parasitic Passive Coupling
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Solution Overview
Problem
Conventional lead frame packages experience performance compromise due to parasitic inductances that grow with distance between passive elements and semiconductor dies, affecting the performance of components like decoupling capacitors, especially in reducing electromagnetic interference.
Innovation Solution
A substrate-on-die package architecture where a passive circuit element, such as an interdigital capacitor, inductor coil, or balun, is mounted directly on the semiconductor die using a routable lead frame, embedded trace substrate, or chip size package, reducing parasitic inductances by minimizing the distance between the passive element and the die, and encapsulated with a molding material along with the die and lead frame.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive elements are placed far from the semiconductor die in conventional lead frame packages, then manufacturing is simpler, but parasitic inductances increase and performance deteriorates
Solution Approach 1:
The patent transitions from a planar arrangement where passive elements are distant from the die to a three-dimensional stacked architecture. The passive element is positioned on a substrate that is mounted directly to the second side of the die, creating a vertical integration that minimizes the distance between the die and passive elements while maintaining manufacturing simplicity through established substrate and lead frame technologies.
2Object-affected harmful factors
If passive elements are mounted close to the semiconductor die, then parasitic inductances are minimized, but device complexity increases
Solution Approach 1:
The patent employs vertical stacking to achieve close proximity between passive elements and the die without complicating the manufacturing process. The substrate carrying the passive element is mounted to the second side of the die, creating a compact three-dimensional structure that minimizes parasitic inductances while using standard substrate and lead frame technologies.
Solution Approach 2:
The substrate acts as an intermediary component that bridges the die and the passive element. This substrate, which can be a routable lead frame substrate or embedded trace substrate, provides a platform for mounting the passive element close to the die while maintaining electrical connections through bond wires or bump bonds, thus reducing parasitic inductances without significantly increasing device complexity.
3Object-affected harmful factors
If substrate-on-die architecture is used, then signal filtering and noise reduction improve, but manufacturing precision requirements increase
Solution Approach 1:
The substrate serves as a mediator that facilitates precise mounting of the passive element relative to the die. By providing a dedicated mounting platform with defined bond pads and trace routing, the substrate enables accurate positioning and electrical connection, thereby achieving improved signal filtering and noise reduction without excessively stringent manufacturing precision requirements.
Solution Approach 2:
The substrate is designed to self-align and self-position during the mounting process. The substrate's bond pads are configured to receive bond wires or bump bonds that connect to corresponding pads on the die, enabling automatic alignment and reducing the need for high-precision manual positioning, thus improving electromagnetic interference protection without demanding extreme manufacturing precision.
Data Source
AI summary
A packaged semiconductor device includes a lead frame and a semiconductor die. The semiconductor die has first and second opposing sides, and the first side of the die is mounted to the lead frame. A first set of bond wires and/or bump bonds are configured to electrically couple the die to the lead frame. A passive circuit element is on a substrate, and the substrate is mounted to the second side of the die. A second set of bond wires and/or bump bonds are configured to electrically couple the passive circuit element to the die. A molding material is configured to encapsulate the passive circuit element, the die, and at least a portion of the lead frame.