Semiconductor Substrate Doping for Uniform Porous Layer Peeling

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Solution Overview

Problem

The existing methods for forming a porous layer on a support substrate for semiconductor devices via anodization result in non-uniform thickness across the substrate plane, affecting the uniformity and efficiency of the semiconductor manufacturing process.

Innovation Solution

Implanting a dopant into the semiconductor substrate to reduce its resistance value, followed by anodization treatment to form a porous layer with controlled thickness and uniformity, allowing for precise control of porosity and formation speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If anodization treatment is applied to form a porous layer on the support substrate, then the porous layer can be formed for subsequent peeling and reuse of the substrate, but the thickness of the porous layer becomes non-uniform across the plane of the substrate

Engineering Contradiction:
Improvepeelability and substrate reuseVSAvoidporous layer thickness uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies a preliminary dopant implantation step before anodization to modify the electrical properties of the substrate. By pre-doping the substrate with phosphorus or arsenic at controlled doses (1×10^15 to 1×10^16 atoms/cm²), the electrical conductivity is enhanced uniformly across the substrate surface, which ensures uniform electric field distribution during subsequent anodization, thereby achieving uniform porous layer thickness while maintaining peelability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the electrical parameter (resistivity) of the substrate by controlling dopant concentration and distribution. By adjusting the dopant type (phosphorus or arsenic), implantation dose, and energy, the substrate's electrical properties are optimized to enable uniform porous layer formation through anodization. The resistivity is controlled within specific ranges (0.1-10 Ωcm) to achieve both uniformity and peelability

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the porous layer thickness is increased to improve peeling efficiency, then the substrate can be peeled more effectively, but the non-uniformity in thickness increases across the substrate plane

Engineering Contradiction:
Improvepeeling efficiencyVSAvoidthickness uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent establishes a feedback mechanism where the dopant implantation parameters are optimized based on the desired porous layer thickness and uniformity requirements. By controlling the dopant dose and energy to achieve specific resistivity ranges, the process self-regulates to produce uniform porous layers at the desired thickness, enabling both high peeling efficiency and thickness uniformity without trade-off

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures a porous layer with uniform thickness and porosity, enhancing the semiconductor device manufacturing process by improving the uniformity and reducing manufacturing costs through the reuse of support substrates.

Implementation Method 1

Implanting a dopant into the semiconductor substrate to reduce its resistance value

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

anodization treatment to form a porous layer with controlled thickness and uniformity

Methodology Applied
Scientific EffectAnodization: Anodising

Data Source

PatentUS20240297146A1Method for manufacturing semiconductor device, method for manufacturing support substrate, and method for peeling substrate
Publication Date: 2024.09.05 KIOXIA CORP
  • US20240297146A1 patent drawing
  • US20240297146A1 patent drawing
  • US20240297146A1 patent drawing

AI summary

According to one embodiment, a method for manufacturing a semiconductor device includes forming, on a substrate, an active layer in which a dopant is implanted; forming a porous layer by making the active layer porous by an anodization treatment; forming a device layer including at least a part of a configuration of the semiconductor device above the porous layer; and cleaving the porous layer to remove the substrate.