Semiconductor Substrate Dummy Pattern Layout for Warpage Control

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Solution Overview

Problem

Current semiconductor devices face challenges in improving reliability and reducing stress during substrate formation, particularly in the integration of complex structures like multi-channel active patterns and gate electrodes, which can lead to warpage and damage.

Innovation Solution

The semiconductor device incorporates a first and second dummy pattern with insulating materials on either side of the substrate, overlapping in the direction, to reduce stress and enhance reliability by providing a buffer during the formation of the power rail and via patterns, using different materials for the insulating films and dummy patterns, and specific shapes like circular, square, or bar shapes for the dummy patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If complex structures like multi-channel active patterns and gate electrodes are integrated, then device functionality and current control capability are improved, but stress and warpage during substrate formation increase

Engineering Contradiction:
Improvedevice reliabilityVSAvoidstress during substrate formation
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The dummy pattern is divided into multiple segments (first dummy pattern and second dummy pattern) positioned at different locations around the active pattern. This segmentation allows stress to be distributed and managed at multiple points, reducing overall warpage while maintaining the complex device structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dummy pattern acts as a counterweight structure with insulating material that balances the stress induced by the complex active pattern and gate electrode integration. By positioning dummy patterns at strategic locations, the structural imbalance and resulting warpage are compensated

Inventive Principle:
Principle #8Anti-weight (Counterweight)

2Manufacturing precision

If multi-channel active patterns with fins or nanowires are formed, then scaling and current control capability are improved, but manufacturing complexity increases

Engineering Contradiction:
Improvescaling precisionVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The dummy pattern is formed in advance during the manufacturing process, before final device assembly. This preliminary action establishes a stable structural foundation that facilitates precise formation of multi-channel active patterns and gate electrodes, enabling better scaling control

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy pattern serves as an intermediary structure that simplifies the manufacturing of complex multi-channel devices. By providing a pre-formed structural framework, it mediates between the substrate and the complex active patterns, making the overall manufacturing process more controllable

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If gate length is increased to improve current control, then current control capability is improved, but device area increases

Engineering Contradiction:
Improvecurrent control capabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Instead of increasing gate length in one dimension, the dummy pattern is positioned in different spatial locations (first and second directions) around the active pattern. This dimensional redistribution allows current control to be enhanced through structural configuration rather than simple size increase, maintaining compact device area

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentEP4525030A1Semiconductor devices
Publication Date: 2025.03.19 SAMSUNG ELECTRONICS CO LTD
  • EP4525030A1 patent drawingFigure 1
  • EP4525030A1 patent drawingFigure 2
  • EP4525030A1 patent drawingFigure 3

AI summary

A semiconductor device may include a first substrate, a lower pattern on a first side of the first substrate, a plurality of sheet patterns on the lower pattern and spaced apart from each other in a first direction, a gate electrode which surrounds portions the plurality of sheet patterns, a source/drain pattern which is on one side of the gate electrode and connected to the plurality of sheet patterns, a power rail which is on a second side of the first substrate, a via pattern which extends through the first substrate in the first direction, and is connected to both the power rail and the source/drain pattern, a first dummy pattern on the via pattern, a second substrate on the first dummy pattern, and a second dummy pattern on a third side of the second substrate that faces the first side of the first substrate.