High Yield Substrate Assembly via Edge Bonding
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Solution Overview
Problem
The use of non-Silicon substrates in integrated circuit fabrication is limited by defects caused by lattice mismatch and thermal expansion differences, which become more pronounced in larger substrates, leading to poor production yield and inefficiencies in existing fabrication processes optimized for Silicon wafers.
Innovation Solution
The creation of high yield substrate assemblies by bonding multiple smaller substrates together, either through edge bonding or forming structures on the substrate surface to relieve thermal stress and interrupt crystal patterns, allowing these assemblies to be processed using equipment designed for larger wafers, thereby increasing the effective size and compatibility with existing manufacturing systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If larger non-Silicon substrates are used, then the effective substrate size increases and compatibility with existing fabrication equipment improves, but defect propagation increases due to lattice mismatch and thermal expansion differences
Solution Approach 1:
The patent divides a large substrate into multiple smaller substrate segments that are processed separately and then assembled together to form a large substrate assembly. This segmentation allows each small segment to be processed independently with fewer defects, while the final assembled structure achieves the desired large size for compatibility with fabrication equipment.
Solution Approach 2:
The patent introduces an intermediary carrier substrate that temporarily holds multiple smaller substrates during processing. This carrier substrate acts as a mediator that enables the handling and processing of multiple small substrates as a unified large structure, allowing compatibility with existing fabrication equipment while maintaining the benefits of smaller individual substrate segments.
2Length of stationary object
If multiple smaller substrates are bonded together to form a large assembly, then the effective substrate size increases and equipment compatibility improves, but the complexity of the substrate structure increases
Solution Approach 1:
The patent segments the large substrate into multiple smaller substrates that are bonded together, allowing each segment to be processed independently. This segmentation reduces the complexity of individual substrate processing while achieving the desired large overall size through assembly.
Solution Approach 2:
The patent extracts the complexity of substrate assembly by separating the substrate creation process from the device fabrication process. Smaller substrates are prepared independently with simpler processes, then assembled into a large structure that interfaces with fabrication equipment, thereby extracting and isolating the complexity to the assembly stage rather than the fabrication stage.
3Reliability
If smaller non-Silicon substrates are used, then defect propagation is reduced and production yield improves, but compatibility with existing fabrication equipment optimized for larger wafers decreases
Solution Approach 1:
The patent merges multiple smaller substrates into a single large substrate assembly that can be processed by existing fabrication equipment. The smaller substrates retain their low-defect characteristics while being combined into a unified structure that interfaces with equipment designed for larger wafers, thus merging the benefits of both small and large substrates.
Solution Approach 2:
The patent uses a carrier substrate as an intermediary that enables smaller substrates to be processed on equipment designed for larger wafers. The carrier substrate mediates between the small substrates and the large-format equipment, allowing the small substrates to benefit from reduced defect propagation while maintaining compatibility with existing fabrication tools.
4Reliability
If lattice mismatch and thermal expansion differences are addressed in larger substrates, then defect propagation increases and production yield decreases, but using smaller substrates reduces defect propagation and improves yield
Solution Approach 1:
The patent segments the large substrate into multiple smaller substrates, thereby reducing the size of individual processing units. This segmentation limits the propagation of defects caused by lattice mismatch and thermal expansion within each small substrate, improving production yield while the assembled structure maintains the necessary large overall size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of integrated circuit devices on larger non-Silicon substrates with reduced defect propagation and improved yield, allowing for efficient use of existing fabrication machinery and processes, thereby enhancing throughput and reducing costs.
Implementation Method 1
The edges of the plurality of the piggyback substrates are bonded to one another
Implementation Method 2
The plurality of structures may be operable to relieve thermal stress across the substrate during the processing
Data Source
AI summary
High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.