Substrate Edge Encapsulation for CMOS and III-V Contamination Control
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Solution Overview
Problem
The challenge in the semiconductor industry is to monolithically integrate different semiconductor materials, such as Si-CMOS and III-V materials, within CMOS circuits without exposing non-CMOS materials to CMOS compatible tools, which can lead to contamination, especially when non-CMOS layers are not confined within oxide wells.
Innovation Solution
A method involving circumferential edge removal of Si-CMOS and III-V semiconductor material portions, followed by deposition of a dielectric material to encapsulate these layers, ensuring the III-V material is unexposed and supported by an adjoining section of the second semiconductor material, thereby preventing contamination during backend processing in semiconductor foundries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If non-CMOS materials (e.g., III-V semiconductor layers) are integrated into CMOS circuits, then functional performance (optoelectronic, RF/wireless applications) is improved, but contamination of CMOS compatible tools occurs when non-CMOS layers are exposed at wafer edges
Solution Approach 1:
The patent applies preliminary action by removing a circumferential edge portion of the substrate before backend processing. This preemptive removal eliminates the exposed edges of non-CMOS layers (such as III-V semiconductor materials) that would otherwise contaminate CMOS compatible tools during subsequent processing steps in semiconductor foundries.
Solution Approach 2:
The patent extracts the problematic circumferential edge portion of the substrate that contains exposed non-CMOS materials. By physically removing this edge portion through circumferential edge removal, the patent separates the contaminating elements from the main substrate, preventing contamination of CMOS tools while retaining the functional areas of the device.
2Object-affected harmful factors
If circumferential edge removal is performed to prevent contamination, then CMOS tool compatibility is improved, but substrate area is reduced
Solution Approach 1:
The patent applies partial action by removing only the necessary circumferential edge portion of the substrate - just enough to eliminate exposed non-CMOS materials at the edges, but not so much as to significantly reduce the functional substrate area. This selective removal balances contamination prevention with area preservation.
3Adaptability or versatility
If different semiconductor materials (Si-CMOS and III-V) are monolithically integrated, then device functionality is improved, but processing complexity increases due to material incompatibility
Solution Approach 1:
The patent converts the harmful exposure of non-CMOS material edges into a beneficial controlled removal process. By intentionally designing the circumferential edge removal step, the patent transforms what would be a contamination problem into a systematic processing step that ensures CMOS tool compatibility while maintaining the benefits of monolithic integration of different semiconductor materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively encapsulates CMOS and non-CMOS materials, reducing III-V material contamination by two orders of magnitude, ensuring compatibility with CMOS tools and maintaining the integrity of the substrate during subsequent processing.
Implementation Method 1
a dielectric material is deposited on the substrate which encapsulates at least the Si-CMOS device layer and the layer of first semiconductor material
Data Source
Figure 1
Figure 2a~2c
Figure 2d~2e
AI summary
A method (200) of encapsulating a substrate (202) is disclosed, in which the substrate has at least the following layers: a CMOS device layer (204), a layer of first semiconductor material (206) different to silicon, and a layer of second semiconductor material (208), the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing (252) a portion of the substrate at the edges; and (ii) depositing (254) a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.