Microelectronic Packaging Substrate With Edge-Traced Spacer for High-Density Interconnections
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Solution Overview
Problem
Existing microelectronic packaging technologies face limitations in stacking chip packages due to the need for interconnecting elements to bridge gaps between packages, which restricts the number of interconnections that can be accommodated on a given substrate size, especially when trying to stack packages with top-surface mounting pads.
Innovation Solution
The solution involves a substrate with conductive elements and terminals on opposing surfaces, along with a spacer element and traces that extend along the edge surface, allowing for the accommodation of microelectronic elements and enabling efficient connection and stacking of packages by defining additional surface areas for interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interconnecting elements are used to bridge gaps between stacked packages, then electrical connection between packages is achieved, but the number of interconnections is limited by the substrate size and gap distance
Solution Approach 1:
The patent transitions from planar interconnections on the substrate surface to three-dimensional interconnections by forming conductive traces through the substrate thickness. This allows interconnections to extend in the vertical dimension, enabling more connections within the same footprint area and reducing the impact of gap distances between stacked packages.
Solution Approach 2:
The patent embeds conductive traces within the substrate structure itself, nesting the interconnection paths inside the substrate volume rather than placing them only on the surface. This nested arrangement allows multiple interconnection layers to coexist within the substrate, increasing the number of available interconnections without increasing the external substrate dimensions.
2Quantity of substance
If substrate size is increased to accommodate more interconnecting elements, then the number of interconnections increases, but the package footprint and space requirements increase
Solution Approach 1:
By utilizing the vertical dimension through the substrate thickness to route conductive traces, the patent effectively increases the available interconnection space without expanding the substrate's horizontal footprint. This allows more interconnections to be packed into the same planar area by distributing them through multiple vertical layers.
Solution Approach 2:
The patent creates a three-dimensional interconnection network within the substrate that utilizes the internal volume of the substrate similar to how porous materials utilize internal space. This internal routing capacity allows numerous interconnections to exist within the substrate bulk, increasing connection density without increasing the external footprint.
3Adaptability or versatility
If stacking contacts are placed outside the overmold area, then package stacking is enabled, but the available area for interconnections is restricted to the limited region outside the overmold
Solution Approach 1:
The patent nests the stacking contacts and their associated interconnections within the overmolded region itself, rather than placing them outside. This nested arrangement utilizes the internal space of the overmold to accommodate the stacking interface, thereby enabling package stacking while maintaining the full substrate surface area for additional interconnections.
Solution Approach 2:
The overmolded region serves multiple functions: it provides mechanical protection and encapsulation while simultaneously housing the stacking contacts and their interconnections. This multi-functional use of the overmold space eliminates the need to reserve separate external areas for stacking, maximizing the available area for both stacking and general interconnections.
Data Source
AI summary
A structure may include a spacer element overlying a first portion of a first surface of a substrate; first terminals at a second surface of the substrate opposite the first surface; and second terminals overlying a third surface of the spacer element facing away from the first surface. Traces extend from the second terminals along an edge surface of the spacer element that extends from the third surface towards the first surface, and may be electrically coupled between the second terminals and the first terminals or electrically conductive elements at the first surface. The spacer element may at least partially define a second portion of the first surface, which is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some of the conductive elements are at the second portion and may permit connection with such microelectronic element.