Package Substrate Embedded Interconnects Electroless Fill
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated packages face limitations in routing density and are costly to fabricate, necessitating a cost-effective solution with higher density connections and a lower profile.
Innovation Solution
A package substrate is designed with a dielectric layer, interconnects, and electroless metal layers, featuring embedded interconnects and cavities with selective electroless copper fill, enabling high-density and fine-pitch connections through semi-additive patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional integrated packages use traditional routing methods, then fabrication cost is controlled, but routing density is limited
Solution Approach 1:
The patent transitions from planar surface routing to three-dimensional embedded routing by forming cavities within the substrate and filling them with conductive material. This dimensional change allows interconnects to be embedded throughout the substrate volume, dramatically increasing routing density without proportionally increasing surface area or fabrication complexity.
Solution Approach 2:
The patent embeds conductive interconnect structures within nested cavities in the substrate. The cavities are formed within the substrate volume, and conductive material is nested within these cavities, creating a hierarchical nested structure that maximizes routing capacity within the available substrate volume.
2Area of stationary object
If conventional integrated packages use standard package sizes, then fabrication is simplified, but real estate usage is excessive
Solution Approach 1:
The patent moves interconnect routing from the two-dimensional surface plane into the three-dimensional volume of the substrate through embedded cavities. This allows high-density routing without increasing the surface footprint, as the additional routing capacity is achieved by utilizing the vertical dimension and substrate depth.
Solution Approach 2:
The patent employs thin dielectric layers and flexible cavity structures that can be formed within the substrate. These thin-film dielectric structures allow for high-density embedded interconnects while maintaining a compact overall package profile and minimizing surface area requirements.
3Length of stationary object
If conventional integrated packages use surface-mounted interconnects, then connectivity is achieved, but profile height is excessive
Solution Approach 1:
The patent embeds conductive interconnects within nested cavities in the substrate, creating a compact nested structure. This nesting approach reduces the overall package profile by integrating interconnects within the substrate volume rather than extending them externally, while maintaining reliable electrical connections through the embedded structure.
Solution Approach 2:
The patent transitions interconnect placement from external surface mounting to internal embedding within the substrate volume. This dimensional relocation reduces the external profile height of the package while establishing reliable electrical connections through the embedded conductive paths within the substrate interior.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves higher routing density and reduced fabrication costs, allowing for more efficient and compact integrated packages with improved connectivity between dies.
Implementation Method 1
a first electroless metal layer is formed in the first cavity
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.