Semiconductor Substrate With Equalized Signal Line Lengths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Stacked semiconductor packages experience deteriorated data processing speed due to signal processing speed differences among the semiconductor chips, resulting from varying signal input and output processing speeds across the chips.
Innovation Solution
A substrate design for semiconductor packages featuring a substrate body with connection pads, signal lines, conductive vias, and ball lands on both surfaces, along with a sub-substrate and gap-maintaining members to ensure uniform signal line lengths and prevent chip tilting, facilitating high-speed data processing by maintaining consistent signal line lengths and connections between semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked semiconductor packages are used to increase data storage capacity, then storage capacity is significantly increased, but data processing speed deteriorates due to signal processing speed differences among chips
Solution Approach 1:
The patent applies local quality by making the signal line lengths equal in specific critical paths (input and output signal lines) while allowing other lines to have different lengths. This selective approach ensures that the most performance-critical signal paths have matched lengths for synchronized processing, while other lines can vary without impacting overall performance.
Solution Approach 2:
The patent changes the parameter of signal line length from variable (in conventional designs) to controlled equal length (in this invention). By adjusting and constraining the length parameter of input and output signal lines to be equal, the patent achieves synchronized signal processing across stacked chips, thereby improving data processing speed while maintaining increased storage capacity.
2Ease of manufacture
If signal lines of different lengths are used in stacked semiconductor packages, then manufacturing is simpler, but signal processing speed varies causing performance degradation
Solution Approach 1:
The patent applies local quality by making the signal line lengths equal in specific critical paths (input and output signal lines) while allowing other lines to have different lengths. This selective approach ensures that the most performance-critical signal paths have matched lengths for synchronized processing, while other lines can vary without impacting overall performance.
Solution Approach 2:
The patent applies partial action by equalizing only the critical input and output signal line lengths rather than all signal lines in the package. This partial equalization focuses manufacturing precision efforts on the most performance-critical paths, achieving the necessary signal synchronization without requiring complete uniformity across all lines, thus balancing manufacturing precision with ease of manufacture.
Data Source
AI summary
The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed.