Package Substrate Film Test Pad Layout for COF Signal Testing
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Solution Overview
Problem
Current chip-on-film (COF) packages face challenges in efficiently testing signal transfer characteristics due to limited space and design constraints, leading to contact defects and reduced test yield, especially with the arrangement of test pads and via patterns.
Innovation Solution
A package substrate film with a specific design featuring a film substrate, redistribution patterns, test patterns, and strategically placed test pads between via patterns, allowing for increased pad sizes and improved spatial utilization, which enhances electrical connection paths and reduces defects during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If test pads are arranged in conventional COF packages with limited space, then package size is reduced, but contact defects increase and test yield decreases
Solution Approach 1:
The patent introduces a multi-layer test pad structure where first test pads are arranged on the first surface and second test pads are arranged on the second surface of the substrate. This three-dimensional arrangement allows test pads to be distributed across multiple layers, increasing the effective testing area without expanding the package footprint, thereby reducing contact defects while maintaining compact size.
Solution Approach 2:
The test pad structure is segmented into first test pads and second test pads located on opposite surfaces of the substrate. This segmentation allows independent optimization of each test pad layer and enables better signal distribution, reducing the likelihood of contact defects in any single layer while improving overall test yield.
2Reliability
If test pads are densely arranged to improve test coverage, then test yield may improve, but contact defects increase due to limited space
Solution Approach 1:
By arranging test pads across multiple layers (first surface and second surface), the patent distributes test coverage requirements across different spatial dimensions. This reduces the density pressure on any single layer, allowing adequate spacing between test pads while achieving comprehensive test coverage, thereby reducing contact defects.
Solution Approach 2:
The patent positions second test pads on the second surface in correspondence with first test pads on the first surface, creating a nested-like arrangement where test structures on one surface align with or correspond to structures on the opposite surface. This coordinated arrangement optimizes signal paths and reduces interference, improving test coverage while minimizing contact defects.
3Area of stationary object
If via patterns are placed closer together to reduce package size, then area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The via pattern structure is segmented into first via patterns and second via patterns located on different surfaces. This segmentation allows independent fabrication and alignment optimization for each via layer, reducing the cumulative alignment errors that would occur in a single dense via array, thereby maintaining manufacturing feasibility while reducing package area.
Solution Approach 2:
By distributing via patterns across multiple layers, the patent reduces the planar density requirement for any single via layer. This multi-layer approach allows via patterns to be placed closer together in three-dimensional space while maintaining adequate spacing and alignment tolerance in each individual layer, reducing manufacturing precision requirements.
Data Source
AI summary
A package substrate film including a film substrate including upper and lower surfaces; a test pattern including an upper test line pattern extending on the upper surface of the film substrate; a lower test line pattern extending on the lower surface of the film substrate; a first test via pattern penetrating the film substrate and connecting the upper test line pattern to the lower test line pattern; a second test via pattern penetrating the film substrate outside the first test via pattern and connecting the upper test line pattern to the lower test line pattern; and a test pad between the first test via pattern and the second test via pattern, the test pad including first test pad at an outer side of the first test via pattern; and second test pad at an inner side of the second test via pattern and facing the first test pad.